GRLIB GRCANFD Model
The GRCANFD model is available in the GRCANFD plugin.
@GRCANFD Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
TimeSource |
*void |
Time source object |
GRCANFD Reference
Properties
| Name | Type | Description |
|---|---|---|
CAP |
uint32_t |
Capability Register |
CAPColdResetValue |
uint32_t |
Capability Register |
CAPForcedBits |
uint32_t |
Capability Register |
CAPForcedFlippedBits |
uint32_t |
Capability Register |
CAPReadMask |
uint32_t |
Capability Register |
CAPResetMask |
uint32_t |
Capability Register |
CAPResetValue |
uint32_t |
Capability Register |
CAPWriteMask |
uint32_t |
Capability Register |
COCTRL |
uint32_t |
CANOpen Control Register |
COCTRLColdResetValue |
uint32_t |
CANOpen Control Register |
COCTRLForcedBits |
uint32_t |
CANOpen Control Register |
COCTRLForcedFlippedBits |
uint32_t |
CANOpen Control Register |
COCTRLReadMask |
uint32_t |
CANOpen Control Register |
COCTRLResetMask |
uint32_t |
CANOpen Control Register |
COCTRLResetValue |
uint32_t |
CANOpen Control Register |
COCTRLWriteMask |
uint32_t |
CANOpen Control Register |
COHBCT |
uint32_t |
CANOpen Heartbeat Count Register |
COHBCTColdResetValue |
uint32_t |
CANOpen Heartbeat Count Register |
COHBCTForcedBits |
uint32_t |
CANOpen Heartbeat Count Register |
COHBCTForcedFlippedBits |
uint32_t |
CANOpen Heartbeat Count Register |
COHBCTReadMask |
uint32_t |
CANOpen Heartbeat Count Register |
COHBCTResetMask |
uint32_t |
CANOpen Heartbeat Count Register |
COHBCTResetValue |
uint32_t |
CANOpen Heartbeat Count Register |
COHBCTWriteMask |
uint32_t |
CANOpen Heartbeat Count Register |
COHBTO |
uint32_t |
CANOpen Heartbeat Timeout Register |
COHBTOColdResetValue |
uint32_t |
CANOpen Heartbeat Timeout Register |
COHBTOForcedBits |
uint32_t |
CANOpen Heartbeat Timeout Register |
COHBTOForcedFlippedBits |
uint32_t |
CANOpen Heartbeat Timeout Register |
COHBTOReadMask |
uint32_t |
CANOpen Heartbeat Timeout Register |
COHBTOResetMask |
uint32_t |
CANOpen Heartbeat Timeout Register |
COHBTOResetValue |
uint32_t |
CANOpen Heartbeat Timeout Register |
COHBTOWriteMask |
uint32_t |
CANOpen Heartbeat Timeout Register |
CONF |
uint32_t |
Configuration Register |
CONFColdResetValue |
uint32_t |
Configuration Register |
CONFForcedBits |
uint32_t |
Configuration Register |
CONFForcedFlippedBits |
uint32_t |
Configuration Register |
CONFReadMask |
uint32_t |
Configuration Register |
CONFResetMask |
uint32_t |
Configuration Register |
CONFResetValue |
uint32_t |
Configuration Register |
CONFWriteMask |
uint32_t |
Configuration Register |
COSTS |
uint32_t |
CANOpen Status Register |
COSTSColdResetValue |
uint32_t |
CANOpen Status Register |
COSTSForcedBits |
uint32_t |
CANOpen Status Register |
COSTSForcedFlippedBits |
uint32_t |
CANOpen Status Register |
COSTSReadMask |
uint32_t |
CANOpen Status Register |
COSTSResetMask |
uint32_t |
CANOpen Status Register |
COSTSResetValue |
uint32_t |
CANOpen Status Register |
COSTSWriteMask |
uint32_t |
CANOpen Status Register |
CTRL |
uint32_t |
Control Register |
CTRLColdResetValue |
uint32_t |
Control Register |
CTRLForcedBits |
uint32_t |
Control Register |
CTRLForcedFlippedBits |
uint32_t |
Control Register |
CTRLReadMask |
uint32_t |
Control Register |
CTRLResetMask |
uint32_t |
Control Register |
CTRLResetValue |
uint32_t |
Control Register |
CTRLWriteMask |
uint32_t |
Control Register |
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
DATABR |
uint32_t |
Data Bit-Rate Configuration Register |
DATABRColdResetValue |
uint32_t |
Data Bit-Rate Configuration Register |
DATABRForcedBits |
uint32_t |
Data Bit-Rate Configuration Register |
DATABRForcedFlippedBits |
uint32_t |
Data Bit-Rate Configuration Register |
DATABRReadMask |
uint32_t |
Data Bit-Rate Configuration Register |
DATABRResetMask |
uint32_t |
Data Bit-Rate Configuration Register |
DATABRResetValue |
uint32_t |
Data Bit-Rate Configuration Register |
DATABRWriteMask |
uint32_t |
Data Bit-Rate Configuration Register |
DELCOMP |
uint32_t |
Transmitter Delay Compensation Register |
DELCOMPColdResetValue |
uint32_t |
Transmitter Delay Compensation Register |
DELCOMPForcedBits |
uint32_t |
Transmitter Delay Compensation Register |
DELCOMPForcedFlippedBits |
uint32_t |
Transmitter Delay Compensation Register |
DELCOMPReadMask |
uint32_t |
Transmitter Delay Compensation Register |
DELCOMPResetMask |
uint32_t |
Transmitter Delay Compensation Register |
DELCOMPResetValue |
uint32_t |
Transmitter Delay Compensation Register |
DELCOMPWriteMask |
uint32_t |
Transmitter Delay Compensation Register |
DescriptorBuffer |
temu_Buff |
Internal: Descriptors already received but not fitting inside the memory-mapped RX circular buffer |
LocalName |
*char |
Local name (in component, if applicable) |
LoggingFlags |
uint64_t |
Flags for logging info |
NOMBR |
uint32_t |
Nominal Bit-Rate Configuration Register |
NOMBRColdResetValue |
uint32_t |
Nominal Bit-Rate Configuration Register |
NOMBRForcedBits |
uint32_t |
Nominal Bit-Rate Configuration Register |
NOMBRForcedFlippedBits |
uint32_t |
Nominal Bit-Rate Configuration Register |
NOMBRReadMask |
uint32_t |
Nominal Bit-Rate Configuration Register |
NOMBRResetMask |
uint32_t |
Nominal Bit-Rate Configuration Register |
NOMBRResetValue |
uint32_t |
Nominal Bit-Rate Configuration Register |
NOMBRWriteMask |
uint32_t |
Nominal Bit-Rate Configuration Register |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
PendingCANOpenResponses |
temu_Buff |
Internal: Pending CANOpen Read PDO responses |
RXADDR |
uint32_t |
Receive Channel Address Register |
RXADDRColdResetValue |
uint32_t |
Receive Channel Address Register |
RXADDRForcedBits |
uint32_t |
Receive Channel Address Register |
RXADDRForcedFlippedBits |
uint32_t |
Receive Channel Address Register |
RXADDRReadMask |
uint32_t |
Receive Channel Address Register |
RXADDRResetMask |
uint32_t |
Receive Channel Address Register |
RXADDRResetValue |
uint32_t |
Receive Channel Address Register |
RXADDRWriteMask |
uint32_t |
Receive Channel Address Register |
RXCTRL |
uint32_t |
Receive Channel Control Register |
RXCTRLColdResetValue |
uint32_t |
Receive Channel Control Register |
RXCTRLForcedBits |
uint32_t |
Receive Channel Control Register |
RXCTRLForcedFlippedBits |
uint32_t |
Receive Channel Control Register |
RXCTRLReadMask |
uint32_t |
Receive Channel Control Register |
RXCTRLResetMask |
uint32_t |
Receive Channel Control Register |
RXCTRLResetValue |
uint32_t |
Receive Channel Control Register |
RXCTRLWriteMask |
uint32_t |
Receive Channel Control Register |
RXIRQ |
uint32_t |
Receive Channel Interrupt Register |
RXIRQColdResetValue |
uint32_t |
Receive Channel Interrupt Register |
RXIRQForcedBits |
uint32_t |
Receive Channel Interrupt Register |
RXIRQForcedFlippedBits |
uint32_t |
Receive Channel Interrupt Register |
RXIRQReadMask |
uint32_t |
Receive Channel Interrupt Register |
RXIRQResetMask |
uint32_t |
Receive Channel Interrupt Register |
RXIRQResetValue |
uint32_t |
Receive Channel Interrupt Register |
RXIRQWriteMask |
uint32_t |
Receive Channel Interrupt Register |
RXRD |
uint32_t |
Receive Channel Read Register |
RXRDColdResetValue |
uint32_t |
Receive Channel Read Register |
RXRDForcedBits |
uint32_t |
Receive Channel Read Register |
RXRDForcedFlippedBits |
uint32_t |
Receive Channel Read Register |
RXRDReadMask |
uint32_t |
Receive Channel Read Register |
RXRDResetMask |
uint32_t |
Receive Channel Read Register |
RXRDResetValue |
uint32_t |
Receive Channel Read Register |
RXRDWriteMask |
uint32_t |
Receive Channel Read Register |
RXSIZE |
uint32_t |
Receive Channel Size Register |
RXSIZEColdResetValue |
uint32_t |
Receive Channel Size Register |
RXSIZEForcedBits |
uint32_t |
Receive Channel Size Register |
RXSIZEForcedFlippedBits |
uint32_t |
Receive Channel Size Register |
RXSIZEReadMask |
uint32_t |
Receive Channel Size Register |
RXSIZEResetMask |
uint32_t |
Receive Channel Size Register |
RXSIZEResetValue |
uint32_t |
Receive Channel Size Register |
RXSIZEWriteMask |
uint32_t |
Receive Channel Size Register |
RXWR |
uint32_t |
Receive Channel Write Register |
RXWRColdResetValue |
uint32_t |
Receive Channel Write Register |
RXWRForcedBits |
uint32_t |
Receive Channel Write Register |
RXWRForcedFlippedBits |
uint32_t |
Receive Channel Write Register |
RXWRReadMask |
uint32_t |
Receive Channel Write Register |
RXWRResetMask |
uint32_t |
Receive Channel Write Register |
RXWRResetValue |
uint32_t |
Receive Channel Write Register |
RXWRWriteMask |
uint32_t |
Receive Channel Write Register |
STAT |
uint32_t |
Status Register |
STATColdResetValue |
uint32_t |
Status Register |
STATForcedBits |
uint32_t |
Status Register |
STATForcedFlippedBits |
uint32_t |
Status Register |
STATReadMask |
uint32_t |
Status Register |
STATResetMask |
uint32_t |
Status Register |
STATResetValue |
uint32_t |
Status Register |
STATWriteMask |
uint32_t |
Status Register |
SYNCCODE |
uint32_t |
SYNC Code Filter Register |
SYNCCODEColdResetValue |
uint32_t |
SYNC Code Filter Register |
SYNCCODEForcedBits |
uint32_t |
SYNC Code Filter Register |
SYNCCODEForcedFlippedBits |
uint32_t |
SYNC Code Filter Register |
SYNCCODEReadMask |
uint32_t |
SYNC Code Filter Register |
SYNCCODEResetMask |
uint32_t |
SYNC Code Filter Register |
SYNCCODEResetValue |
uint32_t |
SYNC Code Filter Register |
SYNCCODEWriteMask |
uint32_t |
SYNC Code Filter Register |
SYNCMASK |
uint32_t |
SYNC Mask Filter Register |
SYNCMASKColdResetValue |
uint32_t |
SYNC Mask Filter Register |
SYNCMASKForcedBits |
uint32_t |
SYNC Mask Filter Register |
SYNCMASKForcedFlippedBits |
uint32_t |
SYNC Mask Filter Register |
SYNCMASKReadMask |
uint32_t |
SYNC Mask Filter Register |
SYNCMASKResetMask |
uint32_t |
SYNC Mask Filter Register |
SYNCMASKResetValue |
uint32_t |
SYNC Mask Filter Register |
SYNCMASKWriteMask |
uint32_t |
SYNC Mask Filter Register |
TXADDR |
uint32_t |
Transmit Channel Address Register |
TXADDRColdResetValue |
uint32_t |
Transmit Channel Address Register |
TXADDRForcedBits |
uint32_t |
Transmit Channel Address Register |
TXADDRForcedFlippedBits |
uint32_t |
Transmit Channel Address Register |
TXADDRReadMask |
uint32_t |
Transmit Channel Address Register |
TXADDRResetMask |
uint32_t |
Transmit Channel Address Register |
TXADDRResetValue |
uint32_t |
Transmit Channel Address Register |
TXADDRWriteMask |
uint32_t |
Transmit Channel Address Register |
TXCTRL |
uint32_t |
Transmit Channel Control Register |
TXCTRLColdResetValue |
uint32_t |
Transmit Channel Control Register |
TXCTRLForcedBits |
uint32_t |
Transmit Channel Control Register |
TXCTRLForcedFlippedBits |
uint32_t |
Transmit Channel Control Register |
TXCTRLReadMask |
uint32_t |
Transmit Channel Control Register |
TXCTRLResetMask |
uint32_t |
Transmit Channel Control Register |
TXCTRLResetValue |
uint32_t |
Transmit Channel Control Register |
TXCTRLWriteMask |
uint32_t |
Transmit Channel Control Register |
TXIRQ |
uint32_t |
Transmit Channel Interrupt Register |
TXIRQColdResetValue |
uint32_t |
Transmit Channel Interrupt Register |
TXIRQForcedBits |
uint32_t |
Transmit Channel Interrupt Register |
TXIRQForcedFlippedBits |
uint32_t |
Transmit Channel Interrupt Register |
TXIRQReadMask |
uint32_t |
Transmit Channel Interrupt Register |
TXIRQResetMask |
uint32_t |
Transmit Channel Interrupt Register |
TXIRQResetValue |
uint32_t |
Transmit Channel Interrupt Register |
TXIRQWriteMask |
uint32_t |
Transmit Channel Interrupt Register |
TXRD |
uint32_t |
Transmit Channel Read Register |
TXRDColdResetValue |
uint32_t |
Transmit Channel Read Register |
TXRDForcedBits |
uint32_t |
Transmit Channel Read Register |
TXRDForcedFlippedBits |
uint32_t |
Transmit Channel Read Register |
TXRDReadMask |
uint32_t |
Transmit Channel Read Register |
TXRDResetMask |
uint32_t |
Transmit Channel Read Register |
TXRDResetValue |
uint32_t |
Transmit Channel Read Register |
TXRDWriteMask |
uint32_t |
Transmit Channel Read Register |
TXSIZE |
uint32_t |
Transmit Channel Size Register |
TXSIZEColdResetValue |
uint32_t |
Transmit Channel Size Register |
TXSIZEForcedBits |
uint32_t |
Transmit Channel Size Register |
TXSIZEForcedFlippedBits |
uint32_t |
Transmit Channel Size Register |
TXSIZEReadMask |
uint32_t |
Transmit Channel Size Register |
TXSIZEResetMask |
uint32_t |
Transmit Channel Size Register |
TXSIZEResetValue |
uint32_t |
Transmit Channel Size Register |
TXSIZEWriteMask |
uint32_t |
Transmit Channel Size Register |
TXWR |
uint32_t |
Transmit Channel Write Register |
TXWRColdResetValue |
uint32_t |
Transmit Channel Write Register |
TXWRForcedBits |
uint32_t |
Transmit Channel Write Register |
TXWRForcedFlippedBits |
uint32_t |
Transmit Channel Write Register |
TXWRReadMask |
uint32_t |
Transmit Channel Write Register |
TXWRResetMask |
uint32_t |
Transmit Channel Write Register |
TXWRResetValue |
uint32_t |
Transmit Channel Write Register |
TXWRWriteMask |
uint32_t |
Transmit Channel Write Register |
TimeSource |
*void |
Time source object |
bus |
temu_IfaceRef/ <unknown> |
CAN (FD) bus. |
config.infiniteBusSpeed |
uint8_t |
Send next CAN-FD frame without delay. |
config.irq |
uint8_t |
Interrupt number |
config.littleEndian |
uint8_t |
Endianess of memory interface. |
config.singleIrq |
uint8_t |
Single interrupt |
irqCtrl |
temu_IfaceRef/ <unknown> |
IRQ controller. |
memAccess |
temu_IfaceRef/ <unknown> |
Memory Interface for DMA containing underlying buffers. |
pnp.bar |
uint32_t |
AMBA plug and play base address register |
pnp.config |
uint32_t |
AMBA plug and play config word |
Limitations
-
There is no arbitration of messages in the message passing simulated world and buses are not synchronized.
-
The model does at present not register filters with the CAN bus model.
-
The CANOpen Heartbeat mechanism is unimplemented. Anything written to or read from CANOpen Heartbeat related registers will be ignored. CANOpen PDOs with a heartbeat function code are acknowleged but do not reset any counters.
-
The model would report a overrun if a frame is received without a RX descriptor beeing available sooner than the hardware if the
rxbufsizeIP configuration option is higher than one.