GRLIB GRCANFD Model

The GRCANFD model is available in the GRCANFD plugin.

Loading the Plugin

import GRCANFD

Configuration

@GRCANFD Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @GRCANFD

new

Create new instance of GRCANFD

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

GRCANFD Reference

Properties

Name Type Description

CAP

uint32_t

Capability Register

CAPColdResetValue

uint32_t

Capability Register

CAPForcedBits

uint32_t

Capability Register

CAPForcedFlippedBits

uint32_t

Capability Register

CAPReadMask

uint32_t

Capability Register

CAPResetMask

uint32_t

Capability Register

CAPResetValue

uint32_t

Capability Register

CAPWriteMask

uint32_t

Capability Register

COCTRL

uint32_t

CANOpen Control Register

COCTRLColdResetValue

uint32_t

CANOpen Control Register

COCTRLForcedBits

uint32_t

CANOpen Control Register

COCTRLForcedFlippedBits

uint32_t

CANOpen Control Register

COCTRLReadMask

uint32_t

CANOpen Control Register

COCTRLResetMask

uint32_t

CANOpen Control Register

COCTRLResetValue

uint32_t

CANOpen Control Register

COCTRLWriteMask

uint32_t

CANOpen Control Register

COHBCT

uint32_t

CANOpen Heartbeat Count Register

COHBCTColdResetValue

uint32_t

CANOpen Heartbeat Count Register

COHBCTForcedBits

uint32_t

CANOpen Heartbeat Count Register

COHBCTForcedFlippedBits

uint32_t

CANOpen Heartbeat Count Register

COHBCTReadMask

uint32_t

CANOpen Heartbeat Count Register

COHBCTResetMask

uint32_t

CANOpen Heartbeat Count Register

COHBCTResetValue

uint32_t

CANOpen Heartbeat Count Register

COHBCTWriteMask

uint32_t

CANOpen Heartbeat Count Register

COHBTO

uint32_t

CANOpen Heartbeat Timeout Register

COHBTOColdResetValue

uint32_t

CANOpen Heartbeat Timeout Register

COHBTOForcedBits

uint32_t

CANOpen Heartbeat Timeout Register

COHBTOForcedFlippedBits

uint32_t

CANOpen Heartbeat Timeout Register

COHBTOReadMask

uint32_t

CANOpen Heartbeat Timeout Register

COHBTOResetMask

uint32_t

CANOpen Heartbeat Timeout Register

COHBTOResetValue

uint32_t

CANOpen Heartbeat Timeout Register

COHBTOWriteMask

uint32_t

CANOpen Heartbeat Timeout Register

CONF

uint32_t

Configuration Register

CONFColdResetValue

uint32_t

Configuration Register

CONFForcedBits

uint32_t

Configuration Register

CONFForcedFlippedBits

uint32_t

Configuration Register

CONFReadMask

uint32_t

Configuration Register

CONFResetMask

uint32_t

Configuration Register

CONFResetValue

uint32_t

Configuration Register

CONFWriteMask

uint32_t

Configuration Register

COSTS

uint32_t

CANOpen Status Register

COSTSColdResetValue

uint32_t

CANOpen Status Register

COSTSForcedBits

uint32_t

CANOpen Status Register

COSTSForcedFlippedBits

uint32_t

CANOpen Status Register

COSTSReadMask

uint32_t

CANOpen Status Register

COSTSResetMask

uint32_t

CANOpen Status Register

COSTSResetValue

uint32_t

CANOpen Status Register

COSTSWriteMask

uint32_t

CANOpen Status Register

CTRL

uint32_t

Control Register

CTRLColdResetValue

uint32_t

Control Register

CTRLForcedBits

uint32_t

Control Register

CTRLForcedFlippedBits

uint32_t

Control Register

CTRLReadMask

uint32_t

Control Register

CTRLResetMask

uint32_t

Control Register

CTRLResetValue

uint32_t

Control Register

CTRLWriteMask

uint32_t

Control Register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

DATABR

uint32_t

Data Bit-Rate Configuration Register

DATABRColdResetValue

uint32_t

Data Bit-Rate Configuration Register

DATABRForcedBits

uint32_t

Data Bit-Rate Configuration Register

DATABRForcedFlippedBits

uint32_t

Data Bit-Rate Configuration Register

DATABRReadMask

uint32_t

Data Bit-Rate Configuration Register

DATABRResetMask

uint32_t

Data Bit-Rate Configuration Register

DATABRResetValue

uint32_t

Data Bit-Rate Configuration Register

DATABRWriteMask

uint32_t

Data Bit-Rate Configuration Register

DELCOMP

uint32_t

Transmitter Delay Compensation Register

DELCOMPColdResetValue

uint32_t

Transmitter Delay Compensation Register

DELCOMPForcedBits

uint32_t

Transmitter Delay Compensation Register

DELCOMPForcedFlippedBits

uint32_t

Transmitter Delay Compensation Register

DELCOMPReadMask

uint32_t

Transmitter Delay Compensation Register

DELCOMPResetMask

uint32_t

Transmitter Delay Compensation Register

DELCOMPResetValue

uint32_t

Transmitter Delay Compensation Register

DELCOMPWriteMask

uint32_t

Transmitter Delay Compensation Register

DescriptorBuffer

temu_Buff

Internal: Descriptors already received but not fitting inside the memory-mapped RX circular buffer

IM

uint32_t

Interrupt Mask Register

IMColdResetValue

uint32_t

Interrupt Mask Register

IMForcedBits

uint32_t

Interrupt Mask Register

IMForcedFlippedBits

uint32_t

Interrupt Mask Register

IMReadMask

uint32_t

Interrupt Mask Register

IMResetMask

uint32_t

Interrupt Mask Register

IMResetValue

uint32_t

Interrupt Mask Register

IMWriteMask

uint32_t

Interrupt Mask Register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

NOMBR

uint32_t

Nominal Bit-Rate Configuration Register

NOMBRColdResetValue

uint32_t

Nominal Bit-Rate Configuration Register

NOMBRForcedBits

uint32_t

Nominal Bit-Rate Configuration Register

NOMBRForcedFlippedBits

uint32_t

Nominal Bit-Rate Configuration Register

NOMBRReadMask

uint32_t

Nominal Bit-Rate Configuration Register

NOMBRResetMask

uint32_t

Nominal Bit-Rate Configuration Register

NOMBRResetValue

uint32_t

Nominal Bit-Rate Configuration Register

NOMBRWriteMask

uint32_t

Nominal Bit-Rate Configuration Register

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

PI

uint32_t

Pending Interrupt Register

PIColdResetValue

uint32_t

Pending Interrupt Register

PIForcedBits

uint32_t

Pending Interrupt Register

PIForcedFlippedBits

uint32_t

Pending Interrupt Register

PIReadMask

uint32_t

Pending Interrupt Register

PIResetMask

uint32_t

Pending Interrupt Register

PIResetValue

uint32_t

Pending Interrupt Register

PIWriteMask

uint32_t

Pending Interrupt Register

PendingCANOpenResponses

temu_Buff

Internal: Pending CANOpen Read PDO responses

RXADDR

uint32_t

Receive Channel Address Register

RXADDRColdResetValue

uint32_t

Receive Channel Address Register

RXADDRForcedBits

uint32_t

Receive Channel Address Register

RXADDRForcedFlippedBits

uint32_t

Receive Channel Address Register

RXADDRReadMask

uint32_t

Receive Channel Address Register

RXADDRResetMask

uint32_t

Receive Channel Address Register

RXADDRResetValue

uint32_t

Receive Channel Address Register

RXADDRWriteMask

uint32_t

Receive Channel Address Register

RXCODE

uint32_t

Receive Channel Acceptance Code Register

RXCODEColdResetValue

uint32_t

Receive Channel Acceptance Code Register

RXCODEForcedBits

uint32_t

Receive Channel Acceptance Code Register

RXCODEForcedFlippedBits

uint32_t

Receive Channel Acceptance Code Register

RXCODEReadMask

uint32_t

Receive Channel Acceptance Code Register

RXCODEResetMask

uint32_t

Receive Channel Acceptance Code Register

RXCODEResetValue

uint32_t

Receive Channel Acceptance Code Register

RXCODEWriteMask

uint32_t

Receive Channel Acceptance Code Register

RXCTRL

uint32_t

Receive Channel Control Register

RXCTRLColdResetValue

uint32_t

Receive Channel Control Register

RXCTRLForcedBits

uint32_t

Receive Channel Control Register

RXCTRLForcedFlippedBits

uint32_t

Receive Channel Control Register

RXCTRLReadMask

uint32_t

Receive Channel Control Register

RXCTRLResetMask

uint32_t

Receive Channel Control Register

RXCTRLResetValue

uint32_t

Receive Channel Control Register

RXCTRLWriteMask

uint32_t

Receive Channel Control Register

RXIRQ

uint32_t

Receive Channel Interrupt Register

RXIRQColdResetValue

uint32_t

Receive Channel Interrupt Register

RXIRQForcedBits

uint32_t

Receive Channel Interrupt Register

RXIRQForcedFlippedBits

uint32_t

Receive Channel Interrupt Register

RXIRQReadMask

uint32_t

Receive Channel Interrupt Register

RXIRQResetMask

uint32_t

Receive Channel Interrupt Register

RXIRQResetValue

uint32_t

Receive Channel Interrupt Register

RXIRQWriteMask

uint32_t

Receive Channel Interrupt Register

RXMASK

uint32_t

Receive Channel Acceptance Mask Register

RXMASKColdResetValue

uint32_t

Receive Channel Acceptance Mask Register

RXMASKForcedBits

uint32_t

Receive Channel Acceptance Mask Register

RXMASKForcedFlippedBits

uint32_t

Receive Channel Acceptance Mask Register

RXMASKReadMask

uint32_t

Receive Channel Acceptance Mask Register

RXMASKResetMask

uint32_t

Receive Channel Acceptance Mask Register

RXMASKResetValue

uint32_t

Receive Channel Acceptance Mask Register

RXMASKWriteMask

uint32_t

Receive Channel Acceptance Mask Register

RXRD

uint32_t

Receive Channel Read Register

RXRDColdResetValue

uint32_t

Receive Channel Read Register

RXRDForcedBits

uint32_t

Receive Channel Read Register

RXRDForcedFlippedBits

uint32_t

Receive Channel Read Register

RXRDReadMask

uint32_t

Receive Channel Read Register

RXRDResetMask

uint32_t

Receive Channel Read Register

RXRDResetValue

uint32_t

Receive Channel Read Register

RXRDWriteMask

uint32_t

Receive Channel Read Register

RXSIZE

uint32_t

Receive Channel Size Register

RXSIZEColdResetValue

uint32_t

Receive Channel Size Register

RXSIZEForcedBits

uint32_t

Receive Channel Size Register

RXSIZEForcedFlippedBits

uint32_t

Receive Channel Size Register

RXSIZEReadMask

uint32_t

Receive Channel Size Register

RXSIZEResetMask

uint32_t

Receive Channel Size Register

RXSIZEResetValue

uint32_t

Receive Channel Size Register

RXSIZEWriteMask

uint32_t

Receive Channel Size Register

RXWR

uint32_t

Receive Channel Write Register

RXWRColdResetValue

uint32_t

Receive Channel Write Register

RXWRForcedBits

uint32_t

Receive Channel Write Register

RXWRForcedFlippedBits

uint32_t

Receive Channel Write Register

RXWRReadMask

uint32_t

Receive Channel Write Register

RXWRResetMask

uint32_t

Receive Channel Write Register

RXWRResetValue

uint32_t

Receive Channel Write Register

RXWRWriteMask

uint32_t

Receive Channel Write Register

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

STAT

uint32_t

Status Register

STATColdResetValue

uint32_t

Status Register

STATForcedBits

uint32_t

Status Register

STATForcedFlippedBits

uint32_t

Status Register

STATReadMask

uint32_t

Status Register

STATResetMask

uint32_t

Status Register

STATResetValue

uint32_t

Status Register

STATWriteMask

uint32_t

Status Register

SYNCCODE

uint32_t

SYNC Code Filter Register

SYNCCODEColdResetValue

uint32_t

SYNC Code Filter Register

SYNCCODEForcedBits

uint32_t

SYNC Code Filter Register

SYNCCODEForcedFlippedBits

uint32_t

SYNC Code Filter Register

SYNCCODEReadMask

uint32_t

SYNC Code Filter Register

SYNCCODEResetMask

uint32_t

SYNC Code Filter Register

SYNCCODEResetValue

uint32_t

SYNC Code Filter Register

SYNCCODEWriteMask

uint32_t

SYNC Code Filter Register

SYNCMASK

uint32_t

SYNC Mask Filter Register

SYNCMASKColdResetValue

uint32_t

SYNC Mask Filter Register

SYNCMASKForcedBits

uint32_t

SYNC Mask Filter Register

SYNCMASKForcedFlippedBits

uint32_t

SYNC Mask Filter Register

SYNCMASKReadMask

uint32_t

SYNC Mask Filter Register

SYNCMASKResetMask

uint32_t

SYNC Mask Filter Register

SYNCMASKResetValue

uint32_t

SYNC Mask Filter Register

SYNCMASKWriteMask

uint32_t

SYNC Mask Filter Register

TXADDR

uint32_t

Transmit Channel Address Register

TXADDRColdResetValue

uint32_t

Transmit Channel Address Register

TXADDRForcedBits

uint32_t

Transmit Channel Address Register

TXADDRForcedFlippedBits

uint32_t

Transmit Channel Address Register

TXADDRReadMask

uint32_t

Transmit Channel Address Register

TXADDRResetMask

uint32_t

Transmit Channel Address Register

TXADDRResetValue

uint32_t

Transmit Channel Address Register

TXADDRWriteMask

uint32_t

Transmit Channel Address Register

TXCTRL

uint32_t

Transmit Channel Control Register

TXCTRLColdResetValue

uint32_t

Transmit Channel Control Register

TXCTRLForcedBits

uint32_t

Transmit Channel Control Register

TXCTRLForcedFlippedBits

uint32_t

Transmit Channel Control Register

TXCTRLReadMask

uint32_t

Transmit Channel Control Register

TXCTRLResetMask

uint32_t

Transmit Channel Control Register

TXCTRLResetValue

uint32_t

Transmit Channel Control Register

TXCTRLWriteMask

uint32_t

Transmit Channel Control Register

TXIRQ

uint32_t

Transmit Channel Interrupt Register

TXIRQColdResetValue

uint32_t

Transmit Channel Interrupt Register

TXIRQForcedBits

uint32_t

Transmit Channel Interrupt Register

TXIRQForcedFlippedBits

uint32_t

Transmit Channel Interrupt Register

TXIRQReadMask

uint32_t

Transmit Channel Interrupt Register

TXIRQResetMask

uint32_t

Transmit Channel Interrupt Register

TXIRQResetValue

uint32_t

Transmit Channel Interrupt Register

TXIRQWriteMask

uint32_t

Transmit Channel Interrupt Register

TXRD

uint32_t

Transmit Channel Read Register

TXRDColdResetValue

uint32_t

Transmit Channel Read Register

TXRDForcedBits

uint32_t

Transmit Channel Read Register

TXRDForcedFlippedBits

uint32_t

Transmit Channel Read Register

TXRDReadMask

uint32_t

Transmit Channel Read Register

TXRDResetMask

uint32_t

Transmit Channel Read Register

TXRDResetValue

uint32_t

Transmit Channel Read Register

TXRDWriteMask

uint32_t

Transmit Channel Read Register

TXSIZE

uint32_t

Transmit Channel Size Register

TXSIZEColdResetValue

uint32_t

Transmit Channel Size Register

TXSIZEForcedBits

uint32_t

Transmit Channel Size Register

TXSIZEForcedFlippedBits

uint32_t

Transmit Channel Size Register

TXSIZEReadMask

uint32_t

Transmit Channel Size Register

TXSIZEResetMask

uint32_t

Transmit Channel Size Register

TXSIZEResetValue

uint32_t

Transmit Channel Size Register

TXSIZEWriteMask

uint32_t

Transmit Channel Size Register

TXWR

uint32_t

Transmit Channel Write Register

TXWRColdResetValue

uint32_t

Transmit Channel Write Register

TXWRForcedBits

uint32_t

Transmit Channel Write Register

TXWRForcedFlippedBits

uint32_t

Transmit Channel Write Register

TXWRReadMask

uint32_t

Transmit Channel Write Register

TXWRResetMask

uint32_t

Transmit Channel Write Register

TXWRResetValue

uint32_t

Transmit Channel Write Register

TXWRWriteMask

uint32_t

Transmit Channel Write Register

TimeSource

*void

Time source object

bus

temu_IfaceRef/ <unknown>

CAN (FD) bus.

config.infiniteBusSpeed

uint8_t

Send next CAN-FD frame without delay.

config.irq

uint8_t

Interrupt number

config.littleEndian

uint8_t

Endianess of memory interface.

config.singleIrq

uint8_t

Single interrupt

irqCtrl

temu_IfaceRef/ <unknown>

IRQ controller.

memAccess

temu_IfaceRef/ <unknown>

Memory Interface for DMA containing underlying buffers.

pnp.bar

uint32_t

AMBA plug and play base address register

pnp.config

uint32_t

AMBA plug and play config word

Interfaces

Name Type Description

ApbIface

ApbIface

APB P&P interface.

CanDevIface

CanDevIface

DeviceIface

DeviceIface

MemAccessIface

MemAccessIface

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

Registers

Register support is currently experimental!

Register Bank Regs

Register CONF
Description

Configuration Register

Reset value

0x00000000

Warm reset mask

0x000000df

Diagram
Field Mask Reset Description

LBS

0x00000080

0x0

Loopback single-shot

LB

0x00000040

0x0

Loopback

SILENT

0x00000010

0x0

Silent mode

SELECT

0x00000008

0x0

Bus select

ENABLE1

0x00000004

0x0

Enable bus 1

ENABLE0

0x00000002

0x0

Enable bus 0

ABORT

0x00000001

0x0

Abort ongoing transfer
Register STAT
Description

Status Register

Reset value

0x00000000

Warm reset mask

0x00ffff3f

Diagram
Field Mask Reset Description

TxErrCntr

0x00ff0000

0x0

Transmit error counter

RxErrCntr

0x0000ff00

0x0

Receive error counter

MD

0x00000020

0x0

Multiple descriptors

ACTIVE

0x00000010

0x0

Active

BMErr

0x00000008

0x0

Bus master error

OR

0x00000004

0x0

Overrun

BusOff

0x00000002

0x0

Bus off

ErrPass

0x00000001

0x0

Error passive
Register CTRL
Description

Control Register

Reset value

0x00000000

Warm reset mask

0x00000001

Diagram
Field Mask Reset Description

RESET

0x00000002

-

Reset

ENABLE

0x00000001

0x0

Enable
Register CAP
Description

Capability Register

Reset value

0xc0000112

Warm reset mask

0xc0000777

Diagram
Field Mask Reset Description

Rev1

0x80000000

0x1

Revision bit 1

Rev2

0x40000000

0x1

Revision bit 2

TxBufSize

0x00000700

0x1

Transmit buffer size

RxBufSize

0x00000070

0x1

Receive buffer size

SepBus

0x00000004

0x0

Separate CAN buses

COpen

0x00000002

0x1

CANOpen support

SingIRQ

0x00000001

0x0

Single IRQ support
Register SYNCMASK
Description

SYNC Mask Filter Register

Reset value

0x1fffffff

Warm reset mask

0x1fffffff

Diagram
Field Mask Reset Description

MASK

0x1fffffff

0x1fffffff

SYNC mask
Register SYNCCODE
Description

SYNC Code Filter Register

Reset value

0x00000000

Warm reset mask

0x1fffffff

Diagram
Field Mask Reset Description

CODE

0x1fffffff

0x0

SYNC code
Register NOMBR
Description

Nominal Bit-Rate Configuration Register

Reset value

0x00000000

Warm reset mask

0x00ffffff

Diagram
Field Mask Reset Description

SCALER

0x00ff0000

0x0

Prescaler

PS1

0x0000fc00

0x0

Phase segment 1

PS2

0x000003f0

0x0

Phase segment 2

SJW

0x0000000f

0x0

Synchronization jump width
Register DATABR
Description

Data Bit-Rate Configuration Register

Reset value

0x00000000

Warm reset mask

0x00ff3def

Diagram
Field Mask Reset Description

SCALER

0x00ff0000

0x0

Prescaler

PS1

0x00003c00

0x0

Phase segment 1

PS2

0x000001e0

0x0

Phase segment 2

SJW

0x0000000f

0x0

Synchronization jump width
Register DELCOMP
Description

Transmitter Delay Compensation Register

Reset value

0x00000000

Warm reset mask

0x0000003f

Diagram
Field Mask Reset Description

TxCompVal

0x0000003f

0x0

Transmitter delay compensation value
Register COCTRL
Description

CANOpen Control Register

Reset value

0x000007f0

Warm reset mask

0x000007f7

Diagram
Field Mask Reset Description

ID

0x000007f0

0x7f

CANOpen node ID

RC

0x00000004

0x0

Remote command

SS

0x00000002

0x0

SYNC single-shot

EN

0x00000001

0x0

CANOpen enable
Register COHBTO
Description

CANOpen Heartbeat Timeout Register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TO

0xffffffff

0x0

Heartbeat timeout
Register COHBCT
Description

CANOpen Heartbeat Count Register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

CT

0xffffffff

0x0

Heartbeat count
Register COSTS
Description

CANOpen Status Register

Reset value

0x00000000

Warm reset mask

0x0000000f

Diagram
Field Mask Reset Description

STS

0x0000000f

0x0

CANOpen status
Register PIMS
Description

Pending Interrupt Masked Status Register

Reset value

0x00000000

Warm reset mask

0x001fffff

Diagram
Field Mask Reset Description

COHbErr

0x00100000

0x0

CANOpen heartbeat error

COSync

0x00080000

0x0

CANOpen SYNC message

COWrCmd

0x00040000

0x0

CANOpen write command

CORdCmd

0x00020000

0x0

CANOpen read command

TxLoss

0x00010000

0x0

Transmit loss

RxMiss

0x00008000

0x0

Receive miss

TxErrCntr

0x00004000

0x0

Transmit error counter threshold

RxErrCntr

0x00002000

0x0

Receive error counter threshold

TxSync

0x00001000

0x0

Transmit synchronization

RxSync

0x00000800

0x0

Receive synchronization

Tx

0x00000400

0x0

Transmit complete

Rx

0x00000200

0x0

Receive complete

TxEmpty

0x00000100

0x0

Transmit channel empty

RxFull

0x00000080

0x0

Receive channel full

TxIRQ

0x00000040

0x0

Transmit channel interrupt

RxIRQ

0x00000020

0x0

Receive channel interrupt

BmRdErr

0x00000010

0x0

Bus master read error

BmWrErr

0x00000008

0x0

Bus master write error

OR

0x00000004

0x0

Overrun

Off

0x00000002

0x0

Bus off

Pass

0x00000001

0x0

Error passive
Register PIM
Description

Pending Interrupt Masked Register

Reset value

0x00000000

Warm reset mask

0x001fffff

Diagram
Field Mask Reset Description

COHbErr

0x00100000

0x0

CANOpen heartbeat error

COSync

0x00080000

0x0

CANOpen SYNC message

COWrCmd

0x00040000

0x0

CANOpen write command

CORdCmd

0x00020000

0x0

CANOpen read command

TxLoss

0x00010000

0x0

Transmit loss

RxMiss

0x00008000

0x0

Receive miss

TxErrCntr

0x00004000

0x0

Transmit error counter threshold

RxErrCntr

0x00002000

0x0

Receive error counter threshold

TxSync

0x00001000

0x0

Transmit synchronization

RxSync

0x00000800

0x0

Receive synchronization

Tx

0x00000400

0x0

Transmit complete

Rx

0x00000200

0x0

Receive complete

TxEmpty

0x00000100

0x0

Transmit channel empty

RxFull

0x00000080

0x0

Receive channel full

TxIRQ

0x00000040

0x0

Transmit channel interrupt

RxIRQ

0x00000020

0x0

Receive channel interrupt

BmRdErr

0x00000010

0x0

Bus master read error

BmWrErr

0x00000008

0x0

Bus master write error

OR

0x00000004

0x0

Overrun

Off

0x00000002

0x0

Bus off

Pass

0x00000001

0x0

Error passive
Register PIS
Description

Pending Interrupt Status Register

Reset value

0x00000000

Warm reset mask

0x001fffff

Diagram
Field Mask Reset Description

COHbErr

0x00100000

0x0

CANOpen heartbeat error

COSync

0x00080000

0x0

CANOpen SYNC message

COWrCmd

0x00040000

0x0

CANOpen write command

CORdCmd

0x00020000

0x0

CANOpen read command

TxLoss

0x00010000

0x0

Transmit loss

RxMiss

0x00008000

0x0

Receive miss

TxErrCntr

0x00004000

0x0

Transmit error counter threshold

RxErrCntr

0x00002000

0x0

Receive error counter threshold

TxSync

0x00001000

0x0

Transmit synchronization

RxSync

0x00000800

0x0

Receive synchronization

Tx

0x00000400

0x0

Transmit complete

Rx

0x00000200

0x0

Receive complete

TxEmpty

0x00000100

0x0

Transmit channel empty

RxFull

0x00000080

0x0

Receive channel full

TxIRQ

0x00000040

0x0

Transmit channel interrupt

RxIRQ

0x00000020

0x0

Receive channel interrupt

BmRdErr

0x00000010

0x0

Bus master read error

BmWrErr

0x00000008

0x0

Bus master write error

OR

0x00000004

0x0

Overrun

Off

0x00000002

0x0

Bus off

Pass

0x00000001

0x0

Error passive
Register PI
Description

Pending Interrupt Register

Reset value

0x00000000

Warm reset mask

0x001fffff

Diagram
Field Mask Reset Description

COHbErr

0x00100000

0x0

CANOpen heartbeat error

COSync

0x00080000

0x0

CANOpen SYNC message

COWrCmd

0x00040000

0x0

CANOpen write command

CORdCmd

0x00020000

0x0

CANOpen read command

TxLoss

0x00010000

0x0

Transmit loss

RxMiss

0x00008000

0x0

Receive miss

TxErrCntr

0x00004000

0x0

Transmit error counter threshold

RxErrCntr

0x00002000

0x0

Receive error counter threshold

TxSync

0x00001000

0x0

Transmit synchronization

RxSync

0x00000800

0x0

Receive synchronization

Tx

0x00000400

0x0

Transmit complete

Rx

0x00000200

0x0

Receive complete

TxEmpty

0x00000100

0x0

Transmit channel empty

RxFull

0x00000080

0x0

Receive channel full

TxIRQ

0x00000040

0x0

Transmit channel interrupt

RxIRQ

0x00000020

0x0

Receive channel interrupt

BmRdErr

0x00000010

0x0

Bus master read error

BmWrErr

0x00000008

0x0

Bus master write error

OR

0x00000004

0x0

Overrun

Off

0x00000002

0x0

Bus off

Pass

0x00000001

0x0

Error passive
Register IM
Description

Interrupt Mask Register

Reset value

0x00000000

Warm reset mask

0x001fffff

Diagram
Field Mask Reset Description

COHbErr

0x00100000

0x0

CANOpen heartbeat error

COSync

0x00080000

0x0

CANOpen SYNC message

COWrCmd

0x00040000

0x0

CANOpen write command

CORdCmd

0x00020000

0x0

CANOpen read command

TxLoss

0x00010000

0x0

Transmit loss

RxMiss

0x00008000

0x0

Receive miss

TxErrCntr

0x00004000

0x0

Transmit error counter threshold

RxErrCntr

0x00002000

0x0

Receive error counter threshold

TxSync

0x00001000

0x0

Transmit synchronization

RxSync

0x00000800

0x0

Receive synchronization

Tx

0x00000400

0x0

Transmit complete

Rx

0x00000200

0x0

Receive complete

TxEmpty

0x00000100

0x0

Transmit channel empty

RxFull

0x00000080

0x0

Receive channel full

TxIRQ

0x00000040

0x0

Transmit channel interrupt

RxIRQ

0x00000020

0x0

Receive channel interrupt

BmRdErr

0x00000010

0x0

Bus master read error

BmWrErr

0x00000008

0x0

Bus master write error

OR

0x00000004

0x0

Overrun

Off

0x00000002

0x0

Bus off

Pass

0x00000001

0x0

Error passive
Register PIC
Description

Pending Interrupt Clear Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

COHbErr

0x00100000

-

CANOpen heartbeat error

COSync

0x00080000

-

CANOpen SYNC message

COWrCmd

0x00040000

-

CANOpen write command

CORdCmd

0x00020000

-

CANOpen read command

TxLoss

0x00010000

-

Transmit loss

RxMiss

0x00008000

-

Receive miss

TxErrCntr

0x00004000

-

Transmit error counter threshold

RxErrCntr

0x00002000

-

Receive error counter threshold

TxSync

0x00001000

-

Transmit synchronization

RxSync

0x00000800

-

Receive synchronization

Tx

0x00000400

-

Transmit complete

Rx

0x00000200

-

Receive complete

TxEmpty

0x00000100

-

Transmit channel empty

RxFull

0x00000080

-

Receive channel full

TxIRQ

0x00000040

-

Transmit channel interrupt

RxIRQ

0x00000020

-

Receive channel interrupt

BmRdErr

0x00000010

-

Bus master read error

BmWrErr

0x00000008

-

Bus master write error

OR

0x00000004

-

Overrun

Off

0x00000002

-

Bus off

Pass

0x00000001

-

Error passive
Register RXMASK
Description

Receive Channel Acceptance Mask Register

Reset value

0x1fffffff

Warm reset mask

0x1fffffff

Diagram
Field Mask Reset Description

AM

0x1fffffff

0x1fffffff

Acceptance mask
Register RXCODE
Description

Receive Channel Acceptance Code Register

Reset value

0x00000000

Warm reset mask

0x1fffffff

Diagram
Field Mask Reset Description

AC

0x1fffffff

0x0

Acceptance code
Register TXCTRL
Description

Transmit Channel Control Register

Reset value

0x00000000

Warm reset mask

0x0000000f

Diagram
Field Mask Reset Description

DisAck

0x00000008

0x0

Disable acknowledge

Single

0x00000004

0x0

Single descriptor

Ongoing

0x00000002

0x0

Transfer ongoing

Enable

0x00000001

0x0

Channel enable
Register TXADDR
Description

Transmit Channel Address Register

Reset value

0x00000000

Warm reset mask

0xfffffc00

Diagram
Field Mask Reset Description

ADDR

0xfffffc00

0x0

Descriptor table address
Register TXSIZE
Description

Transmit Channel Size Register

Reset value

0x00000000

Warm reset mask

0x001fffc0

Diagram
Field Mask Reset Description

SIZE

0x001fffc0

0x0

Descriptor table size
Register TXWR
Description

Transmit Channel Write Register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

WR

0x000ffff0

0x0

Write pointer
Register TXRD
Description

Transmit Channel Read Register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

RD

0x000ffff0

0x0

Read pointer
Register TXIRQ
Description

Transmit Channel Interrupt Register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

IRQ

0x000ffff0

0x0

Interrupt pointer
Register RXCTRL
Description

Receive Channel Control Register

Reset value

0x00000000

Warm reset mask

0x0000000f

Diagram
Field Mask Reset Description

OF

0x00000008

0x0

Overflow

DisAck

0x00000004

0x0

Disable acknowledge

Ongoing

0x00000002

0x0

Transfer ongoing

Enable

0x00000001

0x0

Channel enable
Register RXADDR
Description

Receive Channel Address Register

Reset value

0x00000000

Warm reset mask

0xfffffc00

Diagram
Field Mask Reset Description

ADDR

0xfffffc00

0x0

Descriptor table address
Register RXSIZE
Description

Receive Channel Size Register

Reset value

0x00000000

Warm reset mask

0x001fffc0

Diagram
Field Mask Reset Description

SIZE

0x001fffc0

0x0

Descriptor table size
Register RXWR
Description

Receive Channel Write Register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

WR

0x000ffff0

0x0

Write pointer
Register RXRD
Description

Receive Channel Read Register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

RD

0x000ffff0

0x0

Read pointer
Register RXIRQ
Description

Receive Channel Interrupt Register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

IRQ

0x000ffff0

0x0

Interrupt pointer

Commands

Name Description

delete

Dispose instance of GRCANFD

Limitations

  • There is no arbitration of messages in the message passing simulated world and buses are not synchronized.

  • The model does at present not register filters with the CAN bus model.

  • The CANOpen Heartbeat mechanism is unimplemented. Anything written to or read from CANOpen Heartbeat related registers will be ignored. CANOpen PDOs with a heartbeat function code are acknowleged but do not reset any counters.

  • The model would report a overrun if a frame is received without a RX descriptor beeing available sooner than the hardware if the rxbufsize IP configuration option is higher than one.