GRLIB GRSPFI Model
The GRSPFI device is part of the GRLIB IP library.
It is available in libTEMUGRSPFI.so.
@GRSPFI Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TimeSource |
*void |
Time source object |
GRSPFI Reference
Properties
| Name | Type | Description |
|---|---|---|
BCCONF |
uint32_t |
Broadcast Channel Configuration Register |
BCCONFColdResetValue |
uint32_t |
Broadcast Channel Configuration Register |
BCCONFForcedBits |
uint32_t |
Broadcast Channel Configuration Register |
BCCONFForcedFlippedBits |
uint32_t |
Broadcast Channel Configuration Register |
BCCONFReadMask |
uint32_t |
Broadcast Channel Configuration Register |
BCCONFResetMask |
uint32_t |
Broadcast Channel Configuration Register |
BCCONFResetValue |
uint32_t |
Broadcast Channel Configuration Register |
BCCONFWriteMask |
uint32_t |
Broadcast Channel Configuration Register |
BCMAP |
uint32_t |
Broadcast Channel Mapping Register |
BCMAPColdResetValue |
uint32_t |
Broadcast Channel Mapping Register |
BCMAPForcedBits |
uint32_t |
Broadcast Channel Mapping Register |
BCMAPForcedFlippedBits |
uint32_t |
Broadcast Channel Mapping Register |
BCMAPReadMask |
uint32_t |
Broadcast Channel Mapping Register |
BCMAPResetMask |
uint32_t |
Broadcast Channel Mapping Register |
BCMAPResetValue |
uint32_t |
Broadcast Channel Mapping Register |
BCMAPWriteMask |
uint32_t |
Broadcast Channel Mapping Register |
BCRXADDR |
uint32_t |
Broadcast Channel RX Address Register |
BCRXADDRColdResetValue |
uint32_t |
Broadcast Channel RX Address Register |
BCRXADDRForcedBits |
uint32_t |
Broadcast Channel RX Address Register |
BCRXADDRForcedFlippedBits |
uint32_t |
Broadcast Channel RX Address Register |
BCRXADDRReadMask |
uint32_t |
Broadcast Channel RX Address Register |
BCRXADDRResetMask |
uint32_t |
Broadcast Channel RX Address Register |
BCRXADDRResetValue |
uint32_t |
Broadcast Channel RX Address Register |
BCRXADDRWriteMask |
uint32_t |
Broadcast Channel RX Address Register |
BCRXRPTR |
uint32_t |
Broadcast Channel RX Read Pointer Register |
BCRXRPTRColdResetValue |
uint32_t |
Broadcast Channel RX Read Pointer Register |
BCRXRPTRForcedBits |
uint32_t |
Broadcast Channel RX Read Pointer Register |
BCRXRPTRForcedFlippedBits |
uint32_t |
Broadcast Channel RX Read Pointer Register |
BCRXRPTRReadMask |
uint32_t |
Broadcast Channel RX Read Pointer Register |
BCRXRPTRResetMask |
uint32_t |
Broadcast Channel RX Read Pointer Register |
BCRXRPTRResetValue |
uint32_t |
Broadcast Channel RX Read Pointer Register |
BCRXRPTRWriteMask |
uint32_t |
Broadcast Channel RX Read Pointer Register |
BCRXSIZE |
uint32_t |
Broadcast Channel RX Size Register |
BCRXSIZEColdResetValue |
uint32_t |
Broadcast Channel RX Size Register |
BCRXSIZEForcedBits |
uint32_t |
Broadcast Channel RX Size Register |
BCRXSIZEForcedFlippedBits |
uint32_t |
Broadcast Channel RX Size Register |
BCRXSIZEReadMask |
uint32_t |
Broadcast Channel RX Size Register |
BCRXSIZEResetMask |
uint32_t |
Broadcast Channel RX Size Register |
BCRXSIZEResetValue |
uint32_t |
Broadcast Channel RX Size Register |
BCRXSIZEWriteMask |
uint32_t |
Broadcast Channel RX Size Register |
BCRXWPTR |
uint32_t |
Broadcast Channel RX Write Pointer Register |
BCRXWPTRColdResetValue |
uint32_t |
Broadcast Channel RX Write Pointer Register |
BCRXWPTRForcedBits |
uint32_t |
Broadcast Channel RX Write Pointer Register |
BCRXWPTRForcedFlippedBits |
uint32_t |
Broadcast Channel RX Write Pointer Register |
BCRXWPTRReadMask |
uint32_t |
Broadcast Channel RX Write Pointer Register |
BCRXWPTRResetMask |
uint32_t |
Broadcast Channel RX Write Pointer Register |
BCRXWPTRResetValue |
uint32_t |
Broadcast Channel RX Write Pointer Register |
BCRXWPTRWriteMask |
uint32_t |
Broadcast Channel RX Write Pointer Register |
BCTXADDR |
uint32_t |
Broadcast Channel TX Address Register |
BCTXADDRColdResetValue |
uint32_t |
Broadcast Channel TX Address Register |
BCTXADDRForcedBits |
uint32_t |
Broadcast Channel TX Address Register |
BCTXADDRForcedFlippedBits |
uint32_t |
Broadcast Channel TX Address Register |
BCTXADDRReadMask |
uint32_t |
Broadcast Channel TX Address Register |
BCTXADDRResetMask |
uint32_t |
Broadcast Channel TX Address Register |
BCTXADDRResetValue |
uint32_t |
Broadcast Channel TX Address Register |
BCTXADDRWriteMask |
uint32_t |
Broadcast Channel TX Address Register |
BCTXRPTR |
uint32_t |
Broadcast Channel TX Read Pointer Register |
BCTXRPTRColdResetValue |
uint32_t |
Broadcast Channel TX Read Pointer Register |
BCTXRPTRForcedBits |
uint32_t |
Broadcast Channel TX Read Pointer Register |
BCTXRPTRForcedFlippedBits |
uint32_t |
Broadcast Channel TX Read Pointer Register |
BCTXRPTRReadMask |
uint32_t |
Broadcast Channel TX Read Pointer Register |
BCTXRPTRResetMask |
uint32_t |
Broadcast Channel TX Read Pointer Register |
BCTXRPTRResetValue |
uint32_t |
Broadcast Channel TX Read Pointer Register |
BCTXRPTRWriteMask |
uint32_t |
Broadcast Channel TX Read Pointer Register |
BCTXSIZE |
uint32_t |
Broadcast Channel TX Size Register |
BCTXSIZEColdResetValue |
uint32_t |
Broadcast Channel TX Size Register |
BCTXSIZEForcedBits |
uint32_t |
Broadcast Channel TX Size Register |
BCTXSIZEForcedFlippedBits |
uint32_t |
Broadcast Channel TX Size Register |
BCTXSIZEReadMask |
uint32_t |
Broadcast Channel TX Size Register |
BCTXSIZEResetMask |
uint32_t |
Broadcast Channel TX Size Register |
BCTXSIZEResetValue |
uint32_t |
Broadcast Channel TX Size Register |
BCTXSIZEWriteMask |
uint32_t |
Broadcast Channel TX Size Register |
BCTXWPTR |
uint32_t |
Broadcast Channel TX Write Pointer Register |
BCTXWPTRColdResetValue |
uint32_t |
Broadcast Channel TX Write Pointer Register |
BCTXWPTRForcedBits |
uint32_t |
Broadcast Channel TX Write Pointer Register |
BCTXWPTRForcedFlippedBits |
uint32_t |
Broadcast Channel TX Write Pointer Register |
BCTXWPTRReadMask |
uint32_t |
Broadcast Channel TX Write Pointer Register |
BCTXWPTRResetMask |
uint32_t |
Broadcast Channel TX Write Pointer Register |
BCTXWPTRResetValue |
uint32_t |
Broadcast Channel TX Write Pointer Register |
BCTXWPTRWriteMask |
uint32_t |
Broadcast Channel TX Write Pointer Register |
BUFCAP |
uint32_t |
Codec Buffers Capabilities Register |
BUFCAPColdResetValue |
uint32_t |
Codec Buffers Capabilities Register |
BUFCAPForcedBits |
uint32_t |
Codec Buffers Capabilities Register |
BUFCAPForcedFlippedBits |
uint32_t |
Codec Buffers Capabilities Register |
BUFCAPReadMask |
uint32_t |
Codec Buffers Capabilities Register |
BUFCAPResetMask |
uint32_t |
Codec Buffers Capabilities Register |
BUFCAPResetValue |
uint32_t |
Codec Buffers Capabilities Register |
BUFCAPWriteMask |
uint32_t |
Codec Buffers Capabilities Register |
CCTRL |
uint32_t |
Codec Control Register |
CCTRLColdResetValue |
uint32_t |
Codec Control Register |
CCTRLForcedBits |
uint32_t |
Codec Control Register |
CCTRLForcedFlippedBits |
uint32_t |
Codec Control Register |
CCTRLReadMask |
uint32_t |
Codec Control Register |
CCTRLResetMask |
uint32_t |
Codec Control Register |
CCTRLResetValue |
uint32_t |
Codec Control Register |
CCTRLWriteMask |
uint32_t |
Codec Control Register |
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
DCCTRL_0 |
uint32_t |
DMA Channel Control Register |
DCCTRL_0ColdResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_0ForcedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_0ForcedFlippedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_0ReadMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_0ResetMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_0ResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_0WriteMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_1 |
uint32_t |
DMA Channel Control Register |
DCCTRL_1ColdResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_1ForcedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_1ForcedFlippedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_1ReadMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_1ResetMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_1ResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_1WriteMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_2 |
uint32_t |
DMA Channel Control Register |
DCCTRL_2ColdResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_2ForcedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_2ForcedFlippedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_2ReadMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_2ResetMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_2ResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_2WriteMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_3 |
uint32_t |
DMA Channel Control Register |
DCCTRL_3ColdResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_3ForcedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_3ForcedFlippedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_3ReadMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_3ResetMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_3ResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_3WriteMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_4 |
uint32_t |
DMA Channel Control Register |
DCCTRL_4ColdResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_4ForcedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_4ForcedFlippedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_4ReadMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_4ResetMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_4ResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_4WriteMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_5 |
uint32_t |
DMA Channel Control Register |
DCCTRL_5ColdResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_5ForcedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_5ForcedFlippedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_5ReadMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_5ResetMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_5ResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_5WriteMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_6 |
uint32_t |
DMA Channel Control Register |
DCCTRL_6ColdResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_6ForcedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_6ForcedFlippedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_6ReadMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_6ResetMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_6ResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_6WriteMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_7 |
uint32_t |
DMA Channel Control Register |
DCCTRL_7ColdResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_7ForcedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_7ForcedFlippedBits |
uint32_t |
DMA Channel Control Register |
DCCTRL_7ReadMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_7ResetMask |
uint32_t |
DMA Channel Control Register |
DCCTRL_7ResetValue |
uint32_t |
DMA Channel Control Register |
DCCTRL_7WriteMask |
uint32_t |
DMA Channel Control Register |
DCICTRL_0 |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_0ColdResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_0ForcedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_0ForcedFlippedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_0ReadMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_0ResetMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_0ResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_0WriteMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_1 |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_1ColdResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_1ForcedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_1ForcedFlippedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_1ReadMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_1ResetMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_1ResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_1WriteMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_2 |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_2ColdResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_2ForcedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_2ForcedFlippedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_2ReadMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_2ResetMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_2ResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_2WriteMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_3 |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_3ColdResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_3ForcedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_3ForcedFlippedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_3ReadMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_3ResetMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_3ResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_3WriteMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_4 |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_4ColdResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_4ForcedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_4ForcedFlippedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_4ReadMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_4ResetMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_4ResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_4WriteMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_5 |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_5ColdResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_5ForcedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_5ForcedFlippedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_5ReadMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_5ResetMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_5ResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_5WriteMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_6 |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_6ColdResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_6ForcedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_6ForcedFlippedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_6ReadMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_6ResetMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_6ResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_6WriteMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_7 |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_7ColdResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_7ForcedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_7ForcedFlippedBits |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_7ReadMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_7ResetMask |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_7ResetValue |
uint32_t |
DMA Channel IRQ Control Register |
DCICTRL_7WriteMask |
uint32_t |
DMA Channel IRQ Control Register |
DCMAP_0 |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_0ColdResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_0ForcedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_0ForcedFlippedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_0ReadMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_0ResetMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_0ResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_0WriteMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_1 |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_1ColdResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_1ForcedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_1ForcedFlippedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_1ReadMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_1ResetMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_1ResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_1WriteMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_2 |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_2ColdResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_2ForcedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_2ForcedFlippedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_2ReadMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_2ResetMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_2ResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_2WriteMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_3 |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_3ColdResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_3ForcedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_3ForcedFlippedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_3ReadMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_3ResetMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_3ResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_3WriteMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_4 |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_4ColdResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_4ForcedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_4ForcedFlippedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_4ReadMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_4ResetMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_4ResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_4WriteMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_5 |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_5ColdResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_5ForcedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_5ForcedFlippedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_5ReadMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_5ResetMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_5ResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_5WriteMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_6 |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_6ColdResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_6ForcedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_6ForcedFlippedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_6ReadMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_6ResetMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_6ResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_6WriteMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_7 |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_7ColdResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_7ForcedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_7ForcedFlippedBits |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_7ReadMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_7ResetMask |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_7ResetValue |
uint32_t |
DMA Channel VC Mapping Register |
DCMAP_7WriteMask |
uint32_t |
DMA Channel VC Mapping Register |
DCSTAT2_0 |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_0ColdResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_0ForcedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_0ForcedFlippedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_0ReadMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_0ResetMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_0ResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_0WriteMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_1 |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_1ColdResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_1ForcedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_1ForcedFlippedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_1ReadMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_1ResetMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_1ResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_1WriteMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_2 |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_2ColdResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_2ForcedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_2ForcedFlippedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_2ReadMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_2ResetMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_2ResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_2WriteMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_3 |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_3ColdResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_3ForcedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_3ForcedFlippedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_3ReadMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_3ResetMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_3ResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_3WriteMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_4 |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_4ColdResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_4ForcedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_4ForcedFlippedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_4ReadMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_4ResetMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_4ResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_4WriteMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_5 |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_5ColdResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_5ForcedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_5ForcedFlippedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_5ReadMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_5ResetMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_5ResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_5WriteMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_6 |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_6ColdResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_6ForcedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_6ForcedFlippedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_6ReadMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_6ResetMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_6ResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_6WriteMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_7 |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_7ColdResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_7ForcedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_7ForcedFlippedBits |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_7ReadMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_7ResetMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_7ResetValue |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT2_7WriteMask |
uint32_t |
DMA Channel Extended Status Register |
DCSTAT_0 |
uint32_t |
DMA Channel Status Register |
DCSTAT_0ColdResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_0ForcedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_0ForcedFlippedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_0ReadMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_0ResetMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_0ResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_0WriteMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_1 |
uint32_t |
DMA Channel Status Register |
DCSTAT_1ColdResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_1ForcedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_1ForcedFlippedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_1ReadMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_1ResetMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_1ResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_1WriteMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_2 |
uint32_t |
DMA Channel Status Register |
DCSTAT_2ColdResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_2ForcedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_2ForcedFlippedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_2ReadMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_2ResetMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_2ResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_2WriteMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_3 |
uint32_t |
DMA Channel Status Register |
DCSTAT_3ColdResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_3ForcedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_3ForcedFlippedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_3ReadMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_3ResetMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_3ResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_3WriteMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_4 |
uint32_t |
DMA Channel Status Register |
DCSTAT_4ColdResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_4ForcedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_4ForcedFlippedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_4ReadMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_4ResetMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_4ResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_4WriteMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_5 |
uint32_t |
DMA Channel Status Register |
DCSTAT_5ColdResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_5ForcedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_5ForcedFlippedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_5ReadMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_5ResetMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_5ResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_5WriteMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_6 |
uint32_t |
DMA Channel Status Register |
DCSTAT_6ColdResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_6ForcedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_6ForcedFlippedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_6ReadMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_6ResetMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_6ResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_6WriteMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_7 |
uint32_t |
DMA Channel Status Register |
DCSTAT_7ColdResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_7ForcedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_7ForcedFlippedBits |
uint32_t |
DMA Channel Status Register |
DCSTAT_7ReadMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_7ResetMask |
uint32_t |
DMA Channel Status Register |
DCSTAT_7ResetValue |
uint32_t |
DMA Channel Status Register |
DCSTAT_7WriteMask |
uint32_t |
DMA Channel Status Register |
DEFADDR |
uint32_t |
Default Address Register |
DEFADDRColdResetValue |
uint32_t |
Default Address Register |
DEFADDRForcedBits |
uint32_t |
Default Address Register |
DEFADDRForcedFlippedBits |
uint32_t |
Default Address Register |
DEFADDRReadMask |
uint32_t |
Default Address Register |
DEFADDRResetMask |
uint32_t |
Default Address Register |
DEFADDRResetValue |
uint32_t |
Default Address Register |
DEFADDRWriteMask |
uint32_t |
Default Address Register |
DLCAP |
uint32_t |
DMA Layer Capabilities Register |
DLCAPColdResetValue |
uint32_t |
DMA Layer Capabilities Register |
DLCAPForcedBits |
uint32_t |
DMA Layer Capabilities Register |
DLCAPForcedFlippedBits |
uint32_t |
DMA Layer Capabilities Register |
DLCAPReadMask |
uint32_t |
DMA Layer Capabilities Register |
DLCAPResetMask |
uint32_t |
DMA Layer Capabilities Register |
DLCAPResetValue |
uint32_t |
DMA Layer Capabilities Register |
DLCAPWriteMask |
uint32_t |
DMA Layer Capabilities Register |
DLCTRL |
uint32_t |
DMA Layer Control Register |
DLCTRLColdResetValue |
uint32_t |
DMA Layer Control Register |
DLCTRLForcedBits |
uint32_t |
DMA Layer Control Register |
DLCTRLForcedFlippedBits |
uint32_t |
DMA Layer Control Register |
DLCTRLReadMask |
uint32_t |
DMA Layer Control Register |
DLCTRLResetMask |
uint32_t |
DMA Layer Control Register |
DLCTRLResetValue |
uint32_t |
DMA Layer Control Register |
DLCTRLWriteMask |
uint32_t |
DMA Layer Control Register |
DLSTAT |
uint32_t |
DMA Layer Status Register |
DLSTATColdResetValue |
uint32_t |
DMA Layer Status Register |
DLSTATForcedBits |
uint32_t |
DMA Layer Status Register |
DLSTATForcedFlippedBits |
uint32_t |
DMA Layer Status Register |
DLSTATReadMask |
uint32_t |
DMA Layer Status Register |
DLSTATResetMask |
uint32_t |
DMA Layer Status Register |
DLSTATResetValue |
uint32_t |
DMA Layer Status Register |
DLSTATWriteMask |
uint32_t |
DMA Layer Status Register |
DMAChannels |
[temu_IfaceRef; 8]/ <unknown> |
DMA Channel Interfaces |
GENCAP |
uint32_t |
Codec General Capabilities Register |
GENCAPColdResetValue |
uint32_t |
Codec General Capabilities Register |
GENCAPForcedBits |
uint32_t |
Codec General Capabilities Register |
GENCAPForcedFlippedBits |
uint32_t |
Codec General Capabilities Register |
GENCAPReadMask |
uint32_t |
Codec General Capabilities Register |
GENCAPResetMask |
uint32_t |
Codec General Capabilities Register |
GENCAPResetValue |
uint32_t |
Codec General Capabilities Register |
GENCAPWriteMask |
uint32_t |
Codec General Capabilities Register |
LLSTAT |
uint32_t |
Lane Layer Status Register |
LLSTATColdResetValue |
uint32_t |
Lane Layer Status Register |
LLSTATForcedBits |
uint32_t |
Lane Layer Status Register |
LLSTATForcedFlippedBits |
uint32_t |
Lane Layer Status Register |
LLSTATReadMask |
uint32_t |
Lane Layer Status Register |
LLSTATResetMask |
uint32_t |
Lane Layer Status Register |
LLSTATResetValue |
uint32_t |
Lane Layer Status Register |
LLSTATWriteMask |
uint32_t |
Lane Layer Status Register |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
RLSTAT |
uint32_t |
Retry Layer Status Register |
RLSTATColdResetValue |
uint32_t |
Retry Layer Status Register |
RLSTATForcedBits |
uint32_t |
Retry Layer Status Register |
RLSTATForcedFlippedBits |
uint32_t |
Retry Layer Status Register |
RLSTATReadMask |
uint32_t |
Retry Layer Status Register |
RLSTATResetMask |
uint32_t |
Retry Layer Status Register |
RLSTATResetValue |
uint32_t |
Retry Layer Status Register |
RLSTATWriteMask |
uint32_t |
Retry Layer Status Register |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
SPFIEN |
uint32_t |
SpaceFibre Enable Register |
SPFIENColdResetValue |
uint32_t |
SpaceFibre Enable Register |
SPFIENForcedBits |
uint32_t |
SpaceFibre Enable Register |
SPFIENForcedFlippedBits |
uint32_t |
SpaceFibre Enable Register |
SPFIENReadMask |
uint32_t |
SpaceFibre Enable Register |
SPFIENResetMask |
uint32_t |
SpaceFibre Enable Register |
SPFIENResetValue |
uint32_t |
SpaceFibre Enable Register |
SPFIENWriteMask |
uint32_t |
SpaceFibre Enable Register |
SpfiPort |
temu_IfaceRef/ <unknown> |
SpaceFibre port to the other side of the link. |
TS |
uint32_t |
Time-slot Register |
TSCTRL |
uint32_t |
Time-slot Control Register |
TSCTRLColdResetValue |
uint32_t |
Time-slot Control Register |
TSCTRLForcedBits |
uint32_t |
Time-slot Control Register |
TSCTRLForcedFlippedBits |
uint32_t |
Time-slot Control Register |
TSCTRLReadMask |
uint32_t |
Time-slot Control Register |
TSCTRLResetMask |
uint32_t |
Time-slot Control Register |
TSCTRLResetValue |
uint32_t |
Time-slot Control Register |
TSCTRLWriteMask |
uint32_t |
Time-slot Control Register |
TSColdResetValue |
uint32_t |
Time-slot Register |
TSForcedBits |
uint32_t |
Time-slot Register |
TSForcedFlippedBits |
uint32_t |
Time-slot Register |
TSLEN |
uint32_t |
Time-slot Length Register |
TSLENColdResetValue |
uint32_t |
Time-slot Length Register |
TSLENForcedBits |
uint32_t |
Time-slot Length Register |
TSLENForcedFlippedBits |
uint32_t |
Time-slot Length Register |
TSLENReadMask |
uint32_t |
Time-slot Length Register |
TSLENResetMask |
uint32_t |
Time-slot Length Register |
TSLENResetValue |
uint32_t |
Time-slot Length Register |
TSLENWriteMask |
uint32_t |
Time-slot Length Register |
TSReadMask |
uint32_t |
Time-slot Register |
TSResetMask |
uint32_t |
Time-slot Register |
TSResetValue |
uint32_t |
Time-slot Register |
TSWriteMask |
uint32_t |
Time-slot Register |
TimeSource |
*void |
Time source object |
VCADDR_0 |
uint32_t |
Virtual Channel Address Register |
VCADDR_0ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_0ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_0ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_0ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_0ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_0ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_0WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_1 |
uint32_t |
Virtual Channel Address Register |
VCADDR_10 |
uint32_t |
Virtual Channel Address Register |
VCADDR_10ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_10ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_10ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_10ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_10ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_10ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_10WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_11 |
uint32_t |
Virtual Channel Address Register |
VCADDR_11ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_11ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_11ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_11ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_11ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_11ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_11WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_12 |
uint32_t |
Virtual Channel Address Register |
VCADDR_12ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_12ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_12ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_12ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_12ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_12ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_12WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_13 |
uint32_t |
Virtual Channel Address Register |
VCADDR_13ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_13ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_13ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_13ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_13ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_13ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_13WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_14 |
uint32_t |
Virtual Channel Address Register |
VCADDR_14ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_14ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_14ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_14ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_14ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_14ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_14WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_15 |
uint32_t |
Virtual Channel Address Register |
VCADDR_15ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_15ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_15ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_15ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_15ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_15ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_15WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_16 |
uint32_t |
Virtual Channel Address Register |
VCADDR_16ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_16ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_16ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_16ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_16ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_16ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_16WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_17 |
uint32_t |
Virtual Channel Address Register |
VCADDR_17ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_17ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_17ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_17ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_17ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_17ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_17WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_18 |
uint32_t |
Virtual Channel Address Register |
VCADDR_18ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_18ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_18ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_18ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_18ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_18ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_18WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_19 |
uint32_t |
Virtual Channel Address Register |
VCADDR_19ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_19ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_19ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_19ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_19ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_19ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_19WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_1ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_1ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_1ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_1ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_1ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_1ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_1WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_2 |
uint32_t |
Virtual Channel Address Register |
VCADDR_20 |
uint32_t |
Virtual Channel Address Register |
VCADDR_20ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_20ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_20ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_20ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_20ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_20ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_20WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_21 |
uint32_t |
Virtual Channel Address Register |
VCADDR_21ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_21ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_21ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_21ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_21ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_21ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_21WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_22 |
uint32_t |
Virtual Channel Address Register |
VCADDR_22ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_22ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_22ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_22ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_22ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_22ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_22WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_23 |
uint32_t |
Virtual Channel Address Register |
VCADDR_23ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_23ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_23ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_23ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_23ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_23ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_23WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_24 |
uint32_t |
Virtual Channel Address Register |
VCADDR_24ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_24ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_24ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_24ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_24ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_24ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_24WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_25 |
uint32_t |
Virtual Channel Address Register |
VCADDR_25ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_25ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_25ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_25ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_25ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_25ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_25WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_26 |
uint32_t |
Virtual Channel Address Register |
VCADDR_26ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_26ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_26ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_26ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_26ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_26ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_26WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_27 |
uint32_t |
Virtual Channel Address Register |
VCADDR_27ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_27ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_27ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_27ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_27ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_27ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_27WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_28 |
uint32_t |
Virtual Channel Address Register |
VCADDR_28ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_28ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_28ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_28ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_28ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_28ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_28WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_29 |
uint32_t |
Virtual Channel Address Register |
VCADDR_29ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_29ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_29ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_29ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_29ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_29ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_29WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_2ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_2ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_2ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_2ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_2ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_2ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_2WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_3 |
uint32_t |
Virtual Channel Address Register |
VCADDR_30 |
uint32_t |
Virtual Channel Address Register |
VCADDR_30ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_30ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_30ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_30ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_30ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_30ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_30WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_31 |
uint32_t |
Virtual Channel Address Register |
VCADDR_31ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_31ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_31ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_31ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_31ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_31ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_31WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_3ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_3ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_3ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_3ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_3ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_3ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_3WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_4 |
uint32_t |
Virtual Channel Address Register |
VCADDR_4ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_4ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_4ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_4ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_4ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_4ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_4WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_5 |
uint32_t |
Virtual Channel Address Register |
VCADDR_5ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_5ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_5ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_5ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_5ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_5ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_5WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_6 |
uint32_t |
Virtual Channel Address Register |
VCADDR_6ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_6ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_6ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_6ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_6ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_6ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_6WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_7 |
uint32_t |
Virtual Channel Address Register |
VCADDR_7ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_7ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_7ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_7ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_7ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_7ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_7WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_8 |
uint32_t |
Virtual Channel Address Register |
VCADDR_8ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_8ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_8ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_8ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_8ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_8ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_8WriteMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_9 |
uint32_t |
Virtual Channel Address Register |
VCADDR_9ColdResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_9ForcedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_9ForcedFlippedBits |
uint32_t |
Virtual Channel Address Register |
VCADDR_9ReadMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_9ResetMask |
uint32_t |
Virtual Channel Address Register |
VCADDR_9ResetValue |
uint32_t |
Virtual Channel Address Register |
VCADDR_9WriteMask |
uint32_t |
Virtual Channel Address Register |
VCCTRL_0 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_0ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_0ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_0ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_0ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_0ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_0ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_0WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_1 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_10 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_10ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_10ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_10ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_10ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_10ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_10ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_10WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_11 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_11ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_11ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_11ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_11ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_11ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_11ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_11WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_12 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_12ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_12ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_12ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_12ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_12ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_12ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_12WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_13 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_13ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_13ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_13ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_13ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_13ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_13ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_13WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_14 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_14ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_14ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_14ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_14ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_14ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_14ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_14WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_15 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_15ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_15ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_15ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_15ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_15ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_15ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_15WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_16 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_16ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_16ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_16ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_16ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_16ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_16ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_16WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_17 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_17ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_17ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_17ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_17ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_17ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_17ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_17WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_18 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_18ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_18ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_18ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_18ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_18ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_18ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_18WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_19 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_19ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_19ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_19ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_19ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_19ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_19ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_19WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_1ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_1ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_1ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_1ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_1ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_1ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_1WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_2 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_20 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_20ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_20ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_20ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_20ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_20ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_20ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_20WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_21 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_21ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_21ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_21ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_21ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_21ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_21ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_21WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_22 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_22ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_22ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_22ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_22ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_22ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_22ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_22WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_23 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_23ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_23ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_23ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_23ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_23ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_23ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_23WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_24 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_24ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_24ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_24ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_24ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_24ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_24ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_24WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_25 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_25ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_25ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_25ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_25ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_25ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_25ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_25WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_26 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_26ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_26ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_26ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_26ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_26ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_26ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_26WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_27 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_27ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_27ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_27ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_27ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_27ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_27ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_27WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_28 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_28ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_28ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_28ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_28ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_28ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_28ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_28WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_29 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_29ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_29ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_29ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_29ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_29ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_29ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_29WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_2ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_2ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_2ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_2ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_2ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_2ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_2WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_3 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_30 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_30ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_30ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_30ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_30ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_30ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_30ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_30WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_31 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_31ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_31ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_31ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_31ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_31ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_31ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_31WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_3ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_3ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_3ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_3ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_3ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_3ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_3WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_4 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_4ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_4ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_4ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_4ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_4ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_4ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_4WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_5 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_5ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_5ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_5ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_5ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_5ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_5ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_5WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_6 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_6ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_6ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_6ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_6ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_6ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_6ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_6WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_7 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_7ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_7ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_7ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_7ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_7ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_7ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_7WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_8 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_8ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_8ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_8ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_8ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_8ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_8ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_8WriteMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_9 |
uint32_t |
Virtual Channel Control Register |
VCCTRL_9ColdResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_9ForcedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_9ForcedFlippedBits |
uint32_t |
Virtual Channel Control Register |
VCCTRL_9ReadMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_9ResetMask |
uint32_t |
Virtual Channel Control Register |
VCCTRL_9ResetValue |
uint32_t |
Virtual Channel Control Register |
VCCTRL_9WriteMask |
uint32_t |
Virtual Channel Control Register |
VCDCTRL_0 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_0ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_0ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_0ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_0ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_0ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_0ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_0WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_1 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_10 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_10ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_10ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_10ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_10ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_10ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_10ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_10WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_11 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_11ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_11ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_11ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_11ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_11ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_11ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_11WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_12 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_12ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_12ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_12ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_12ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_12ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_12ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_12WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_13 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_13ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_13ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_13ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_13ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_13ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_13ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_13WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_14 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_14ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_14ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_14ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_14ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_14ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_14ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_14WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_15 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_15ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_15ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_15ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_15ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_15ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_15ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_15WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_16 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_16ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_16ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_16ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_16ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_16ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_16ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_16WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_17 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_17ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_17ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_17ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_17ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_17ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_17ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_17WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_18 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_18ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_18ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_18ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_18ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_18ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_18ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_18WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_19 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_19ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_19ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_19ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_19ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_19ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_19ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_19WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_1ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_1ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_1ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_1ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_1ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_1ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_1WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_2 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_20 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_20ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_20ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_20ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_20ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_20ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_20ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_20WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_21 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_21ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_21ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_21ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_21ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_21ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_21ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_21WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_22 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_22ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_22ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_22ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_22ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_22ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_22ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_22WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_23 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_23ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_23ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_23ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_23ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_23ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_23ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_23WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_24 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_24ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_24ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_24ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_24ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_24ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_24ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_24WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_25 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_25ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_25ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_25ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_25ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_25ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_25ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_25WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_26 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_26ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_26ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_26ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_26ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_26ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_26ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_26WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_27 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_27ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_27ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_27ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_27ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_27ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_27ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_27WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_28 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_28ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_28ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_28ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_28ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_28ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_28ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_28WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_29 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_29ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_29ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_29ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_29ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_29ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_29ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_29WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_2ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_2ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_2ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_2ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_2ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_2ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_2WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_3 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_30 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_30ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_30ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_30ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_30ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_30ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_30ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_30WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_31 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_31ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_31ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_31ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_31ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_31ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_31ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_31WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_3ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_3ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_3ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_3ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_3ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_3ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_3WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_4 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_4ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_4ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_4ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_4ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_4ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_4ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_4WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_5 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_5ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_5ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_5ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_5ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_5ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_5ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_5WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_6 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_6ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_6ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_6ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_6ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_6ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_6ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_6WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_7 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_7ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_7ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_7ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_7ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_7ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_7ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_7WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_8 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_8ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_8ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_8ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_8ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_8ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_8ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_8WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_9 |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_9ColdResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_9ForcedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_9ForcedFlippedBits |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_9ReadMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_9ResetMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_9ResetValue |
uint32_t |
Virtual Channel Descriptor Control Register |
VCDCTRL_9WriteMask |
uint32_t |
Virtual Channel Descriptor Control Register |
VCKEY_0 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_0ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_0ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_0ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_0ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_0ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_0ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_0WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_1 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_10 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_10ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_10ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_10ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_10ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_10ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_10ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_10WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_11 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_11ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_11ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_11ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_11ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_11ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_11ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_11WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_12 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_12ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_12ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_12ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_12ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_12ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_12ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_12WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_13 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_13ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_13ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_13ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_13ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_13ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_13ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_13WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_14 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_14ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_14ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_14ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_14ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_14ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_14ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_14WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_15 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_15ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_15ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_15ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_15ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_15ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_15ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_15WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_16 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_16ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_16ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_16ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_16ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_16ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_16ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_16WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_17 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_17ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_17ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_17ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_17ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_17ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_17ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_17WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_18 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_18ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_18ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_18ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_18ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_18ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_18ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_18WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_19 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_19ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_19ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_19ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_19ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_19ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_19ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_19WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_1ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_1ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_1ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_1ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_1ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_1ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_1WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_2 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_20 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_20ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_20ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_20ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_20ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_20ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_20ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_20WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_21 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_21ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_21ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_21ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_21ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_21ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_21ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_21WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_22 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_22ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_22ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_22ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_22ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_22ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_22ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_22WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_23 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_23ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_23ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_23ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_23ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_23ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_23ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_23WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_24 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_24ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_24ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_24ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_24ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_24ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_24ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_24WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_25 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_25ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_25ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_25ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_25ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_25ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_25ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_25WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_26 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_26ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_26ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_26ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_26ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_26ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_26ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_26WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_27 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_27ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_27ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_27ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_27ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_27ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_27ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_27WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_28 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_28ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_28ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_28ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_28ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_28ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_28ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_28WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_29 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_29ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_29ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_29ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_29ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_29ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_29ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_29WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_2ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_2ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_2ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_2ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_2ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_2ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_2WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_3 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_30 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_30ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_30ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_30ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_30ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_30ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_30ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_30WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_31 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_31ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_31ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_31ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_31ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_31ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_31ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_31WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_3ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_3ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_3ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_3ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_3ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_3ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_3WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_4 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_4ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_4ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_4ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_4ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_4ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_4ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_4WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_5 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_5ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_5ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_5ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_5ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_5ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_5ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_5WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_6 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_6ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_6ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_6ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_6ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_6ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_6ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_6WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_7 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_7ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_7ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_7ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_7ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_7ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_7ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_7WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_8 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_8ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_8ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_8ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_8ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_8ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_8ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_8WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_9 |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_9ColdResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_9ForcedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_9ForcedFlippedBits |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_9ReadMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_9ResetMask |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_9ResetValue |
uint32_t |
Virtual Channel Destination Key Register |
VCKEY_9WriteMask |
uint32_t |
Virtual Channel Destination Key Register |
VCMAXLEN_0 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_0ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_0ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_0ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_0ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_0ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_0ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_0WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_1 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_10 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_10ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_10ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_10ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_10ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_10ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_10ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_10WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_11 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_11ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_11ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_11ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_11ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_11ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_11ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_11WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_12 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_12ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_12ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_12ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_12ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_12ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_12ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_12WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_13 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_13ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_13ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_13ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_13ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_13ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_13ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_13WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_14 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_14ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_14ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_14ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_14ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_14ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_14ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_14WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_15 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_15ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_15ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_15ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_15ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_15ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_15ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_15WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_16 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_16ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_16ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_16ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_16ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_16ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_16ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_16WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_17 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_17ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_17ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_17ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_17ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_17ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_17ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_17WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_18 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_18ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_18ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_18ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_18ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_18ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_18ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_18WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_19 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_19ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_19ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_19ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_19ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_19ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_19ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_19WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_1ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_1ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_1ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_1ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_1ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_1ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_1WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_2 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_20 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_20ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_20ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_20ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_20ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_20ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_20ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_20WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_21 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_21ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_21ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_21ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_21ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_21ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_21ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_21WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_22 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_22ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_22ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_22ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_22ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_22ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_22ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_22WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_23 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_23ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_23ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_23ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_23ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_23ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_23ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_23WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_24 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_24ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_24ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_24ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_24ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_24ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_24ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_24WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_25 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_25ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_25ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_25ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_25ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_25ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_25ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_25WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_26 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_26ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_26ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_26ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_26ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_26ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_26ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_26WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_27 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_27ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_27ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_27ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_27ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_27ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_27ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_27WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_28 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_28ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_28ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_28ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_28ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_28ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_28ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_28WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_29 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_29ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_29ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_29ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_29ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_29ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_29ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_29WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_2ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_2ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_2ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_2ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_2ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_2ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_2WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_3 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_30 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_30ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_30ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_30ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_30ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_30ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_30ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_30WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_31 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_31ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_31ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_31ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_31ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_31ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_31ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_31WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_3ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_3ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_3ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_3ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_3ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_3ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_3WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_4 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_4ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_4ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_4ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_4ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_4ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_4ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_4WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_5 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_5ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_5ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_5ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_5ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_5ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_5ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_5WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_6 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_6ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_6ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_6ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_6ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_6ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_6ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_6WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_7 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_7ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_7ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_7ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_7ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_7ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_7ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_7WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_8 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_8ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_8ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_8ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_8ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_8ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_8ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_8WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_9 |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_9ColdResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_9ForcedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_9ForcedFlippedBits |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_9ReadMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_9ResetMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_9ResetValue |
uint32_t |
Virtual Channel RX Max Length Register |
VCMAXLEN_9WriteMask |
uint32_t |
Virtual Channel RX Max Length Register |
VCRXDADDR_0 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_0ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_0ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_0ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_0ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_0ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_0ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_0WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_1 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_10 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_10ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_10ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_10ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_10ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_10ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_10ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_10WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_11 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_11ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_11ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_11ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_11ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_11ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_11ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_11WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_12 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_12ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_12ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_12ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_12ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_12ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_12ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_12WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_13 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_13ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_13ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_13ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_13ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_13ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_13ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_13WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_14 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_14ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_14ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_14ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_14ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_14ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_14ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_14WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_15 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_15ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_15ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_15ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_15ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_15ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_15ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_15WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_16 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_16ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_16ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_16ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_16ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_16ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_16ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_16WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_17 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_17ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_17ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_17ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_17ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_17ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_17ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_17WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_18 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_18ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_18ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_18ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_18ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_18ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_18ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_18WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_19 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_19ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_19ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_19ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_19ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_19ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_19ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_19WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_1ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_1ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_1ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_1ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_1ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_1ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_1WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_2 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_20 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_20ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_20ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_20ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_20ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_20ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_20ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_20WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_21 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_21ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_21ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_21ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_21ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_21ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_21ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_21WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_22 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_22ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_22ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_22ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_22ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_22ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_22ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_22WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_23 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_23ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_23ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_23ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_23ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_23ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_23ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_23WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_24 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_24ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_24ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_24ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_24ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_24ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_24ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_24WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_25 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_25ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_25ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_25ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_25ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_25ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_25ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_25WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_26 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_26ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_26ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_26ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_26ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_26ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_26ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_26WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_27 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_27ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_27ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_27ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_27ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_27ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_27ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_27WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_28 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_28ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_28ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_28ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_28ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_28ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_28ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_28WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_29 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_29ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_29ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_29ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_29ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_29ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_29ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_29WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_2ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_2ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_2ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_2ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_2ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_2ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_2WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_3 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_30 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_30ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_30ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_30ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_30ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_30ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_30ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_30WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_31 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_31ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_31ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_31ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_31ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_31ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_31ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_31WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_3ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_3ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_3ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_3ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_3ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_3ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_3WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_4 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_4ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_4ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_4ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_4ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_4ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_4ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_4WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_5 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_5ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_5ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_5ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_5ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_5ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_5ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_5WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_6 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_6ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_6ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_6ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_6ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_6ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_6ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_6WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_7 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_7ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_7ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_7ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_7ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_7ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_7ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_7WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_8 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_8ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_8ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_8ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_8ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_8ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_8ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_8WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_9 |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_9ColdResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_9ForcedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_9ForcedFlippedBits |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_9ReadMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_9ResetMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_9ResetValue |
uint32_t |
VC RX Descriptor Table Address Register |
VCRXDADDR_9WriteMask |
uint32_t |
VC RX Descriptor Table Address Register |
VCSTAT_0 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_0ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_0ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_0ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_0ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_0ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_0ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_0WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_1 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_10 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_10ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_10ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_10ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_10ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_10ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_10ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_10WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_11 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_11ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_11ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_11ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_11ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_11ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_11ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_11WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_12 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_12ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_12ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_12ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_12ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_12ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_12ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_12WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_13 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_13ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_13ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_13ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_13ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_13ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_13ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_13WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_14 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_14ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_14ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_14ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_14ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_14ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_14ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_14WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_15 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_15ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_15ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_15ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_15ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_15ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_15ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_15WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_16 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_16ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_16ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_16ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_16ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_16ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_16ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_16WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_17 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_17ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_17ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_17ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_17ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_17ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_17ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_17WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_18 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_18ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_18ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_18ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_18ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_18ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_18ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_18WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_19 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_19ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_19ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_19ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_19ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_19ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_19ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_19WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_1ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_1ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_1ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_1ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_1ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_1ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_1WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_2 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_20 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_20ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_20ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_20ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_20ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_20ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_20ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_20WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_21 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_21ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_21ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_21ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_21ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_21ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_21ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_21WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_22 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_22ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_22ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_22ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_22ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_22ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_22ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_22WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_23 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_23ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_23ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_23ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_23ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_23ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_23ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_23WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_24 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_24ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_24ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_24ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_24ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_24ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_24ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_24WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_25 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_25ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_25ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_25ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_25ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_25ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_25ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_25WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_26 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_26ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_26ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_26ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_26ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_26ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_26ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_26WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_27 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_27ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_27ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_27ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_27ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_27ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_27ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_27WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_28 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_28ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_28ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_28ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_28ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_28ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_28ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_28WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_29 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_29ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_29ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_29ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_29ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_29ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_29ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_29WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_2ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_2ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_2ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_2ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_2ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_2ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_2WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_3 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_30 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_30ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_30ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_30ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_30ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_30ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_30ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_30WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_31 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_31ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_31ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_31ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_31ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_31ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_31ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_31WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_3ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_3ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_3ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_3ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_3ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_3ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_3WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_4 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_4ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_4ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_4ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_4ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_4ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_4ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_4WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_5 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_5ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_5ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_5ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_5ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_5ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_5ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_5WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_6 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_6ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_6ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_6ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_6ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_6ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_6ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_6WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_7 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_7ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_7ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_7ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_7ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_7ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_7ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_7WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_8 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_8ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_8ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_8ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_8ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_8ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_8ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_8WriteMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_9 |
uint32_t |
Virtual Channel Status Register |
VCSTAT_9ColdResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_9ForcedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_9ForcedFlippedBits |
uint32_t |
Virtual Channel Status Register |
VCSTAT_9ReadMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_9ResetMask |
uint32_t |
Virtual Channel Status Register |
VCSTAT_9ResetValue |
uint32_t |
Virtual Channel Status Register |
VCSTAT_9WriteMask |
uint32_t |
Virtual Channel Status Register |
VCTS1_0 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_0ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_0ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_0ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_0ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_0ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_0ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_0WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_1 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_10 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_10ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_10ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_10ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_10ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_10ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_10ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_10WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_11 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_11ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_11ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_11ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_11ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_11ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_11ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_11WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_12 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_12ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_12ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_12ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_12ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_12ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_12ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_12WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_13 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_13ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_13ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_13ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_13ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_13ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_13ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_13WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_14 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_14ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_14ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_14ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_14ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_14ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_14ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_14WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_15 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_15ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_15ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_15ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_15ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_15ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_15ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_15WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_16 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_16ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_16ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_16ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_16ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_16ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_16ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_16WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_17 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_17ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_17ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_17ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_17ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_17ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_17ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_17WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_18 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_18ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_18ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_18ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_18ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_18ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_18ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_18WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_19 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_19ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_19ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_19ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_19ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_19ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_19ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_19WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_1ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_1ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_1ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_1ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_1ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_1ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_1WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_2 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_20 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_20ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_20ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_20ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_20ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_20ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_20ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_20WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_21 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_21ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_21ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_21ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_21ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_21ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_21ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_21WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_22 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_22ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_22ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_22ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_22ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_22ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_22ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_22WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_23 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_23ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_23ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_23ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_23ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_23ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_23ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_23WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_24 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_24ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_24ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_24ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_24ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_24ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_24ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_24WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_25 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_25ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_25ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_25ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_25ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_25ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_25ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_25WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_26 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_26ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_26ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_26ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_26ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_26ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_26ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_26WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_27 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_27ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_27ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_27ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_27ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_27ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_27ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_27WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_28 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_28ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_28ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_28ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_28ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_28ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_28ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_28WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_29 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_29ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_29ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_29ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_29ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_29ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_29ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_29WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_2ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_2ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_2ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_2ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_2ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_2ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_2WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_3 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_30 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_30ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_30ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_30ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_30ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_30ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_30ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_30WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_31 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_31ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_31ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_31ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_31ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_31ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_31ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_31WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_3ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_3ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_3ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_3ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_3ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_3ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_3WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_4 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_4ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_4ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_4ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_4ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_4ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_4ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_4WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_5 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_5ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_5ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_5ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_5ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_5ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_5ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_5WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_6 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_6ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_6ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_6ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_6ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_6ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_6ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_6WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_7 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_7ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_7ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_7ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_7ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_7ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_7ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_7WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_8 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_8ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_8ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_8ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_8ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_8ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_8ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_8WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_9 |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_9ColdResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_9ForcedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_9ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_9ReadMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_9ResetMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_9ResetValue |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS1_9WriteMask |
uint32_t |
Virtual Channel Time-slot 1 Register |
VCTS2_0 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_0ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_0ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_0ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_0ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_0ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_0ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_0WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_1 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_10 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_10ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_10ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_10ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_10ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_10ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_10ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_10WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_11 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_11ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_11ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_11ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_11ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_11ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_11ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_11WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_12 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_12ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_12ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_12ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_12ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_12ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_12ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_12WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_13 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_13ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_13ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_13ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_13ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_13ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_13ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_13WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_14 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_14ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_14ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_14ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_14ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_14ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_14ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_14WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_15 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_15ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_15ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_15ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_15ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_15ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_15ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_15WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_16 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_16ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_16ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_16ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_16ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_16ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_16ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_16WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_17 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_17ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_17ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_17ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_17ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_17ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_17ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_17WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_18 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_18ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_18ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_18ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_18ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_18ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_18ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_18WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_19 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_19ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_19ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_19ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_19ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_19ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_19ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_19WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_1ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_1ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_1ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_1ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_1ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_1ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_1WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_2 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_20 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_20ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_20ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_20ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_20ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_20ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_20ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_20WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_21 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_21ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_21ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_21ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_21ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_21ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_21ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_21WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_22 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_22ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_22ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_22ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_22ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_22ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_22ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_22WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_23 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_23ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_23ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_23ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_23ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_23ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_23ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_23WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_24 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_24ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_24ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_24ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_24ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_24ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_24ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_24WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_25 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_25ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_25ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_25ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_25ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_25ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_25ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_25WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_26 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_26ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_26ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_26ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_26ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_26ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_26ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_26WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_27 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_27ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_27ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_27ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_27ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_27ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_27ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_27WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_28 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_28ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_28ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_28ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_28ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_28ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_28ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_28WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_29 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_29ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_29ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_29ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_29ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_29ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_29ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_29WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_2ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_2ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_2ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_2ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_2ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_2ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_2WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_3 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_30 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_30ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_30ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_30ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_30ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_30ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_30ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_30WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_31 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_31ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_31ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_31ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_31ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_31ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_31ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_31WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_3ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_3ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_3ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_3ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_3ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_3ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_3WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_4 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_4ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_4ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_4ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_4ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_4ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_4ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_4WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_5 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_5ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_5ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_5ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_5ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_5ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_5ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_5WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_6 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_6ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_6ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_6ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_6ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_6ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_6ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_6WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_7 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_7ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_7ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_7ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_7ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_7ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_7ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_7WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_8 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_8ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_8ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_8ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_8ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_8ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_8ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_8WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_9 |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_9ColdResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_9ForcedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_9ForcedFlippedBits |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_9ReadMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_9ResetMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_9ResetValue |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTS2_9WriteMask |
uint32_t |
Virtual Channel Time-slot 2 Register |
VCTXDADDR_0 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_0ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_0ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_0ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_0ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_0ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_0ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_0WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_1 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_10 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_10ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_10ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_10ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_10ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_10ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_10ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_10WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_11 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_11ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_11ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_11ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_11ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_11ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_11ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_11WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_12 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_12ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_12ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_12ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_12ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_12ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_12ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_12WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_13 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_13ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_13ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_13ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_13ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_13ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_13ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_13WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_14 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_14ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_14ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_14ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_14ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_14ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_14ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_14WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_15 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_15ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_15ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_15ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_15ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_15ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_15ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_15WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_16 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_16ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_16ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_16ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_16ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_16ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_16ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_16WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_17 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_17ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_17ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_17ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_17ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_17ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_17ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_17WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_18 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_18ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_18ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_18ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_18ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_18ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_18ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_18WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_19 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_19ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_19ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_19ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_19ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_19ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_19ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_19WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_1ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_1ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_1ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_1ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_1ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_1ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_1WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_2 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_20 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_20ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_20ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_20ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_20ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_20ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_20ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_20WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_21 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_21ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_21ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_21ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_21ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_21ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_21ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_21WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_22 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_22ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_22ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_22ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_22ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_22ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_22ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_22WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_23 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_23ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_23ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_23ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_23ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_23ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_23ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_23WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_24 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_24ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_24ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_24ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_24ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_24ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_24ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_24WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_25 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_25ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_25ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_25ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_25ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_25ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_25ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_25WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_26 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_26ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_26ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_26ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_26ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_26ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_26ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_26WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_27 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_27ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_27ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_27ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_27ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_27ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_27ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_27WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_28 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_28ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_28ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_28ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_28ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_28ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_28ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_28WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_29 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_29ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_29ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_29ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_29ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_29ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_29ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_29WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_2ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_2ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_2ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_2ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_2ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_2ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_2WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_3 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_30 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_30ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_30ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_30ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_30ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_30ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_30ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_30WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_31 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_31ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_31ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_31ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_31ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_31ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_31ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_31WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_3ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_3ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_3ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_3ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_3ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_3ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_3WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_4 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_4ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_4ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_4ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_4ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_4ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_4ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_4WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_5 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_5ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_5ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_5ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_5ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_5ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_5ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_5WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_6 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_6ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_6ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_6ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_6ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_6ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_6ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_6WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_7 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_7ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_7ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_7ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_7ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_7ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_7ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_7WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_8 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_8ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_8ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_8ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_8ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_8ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_8ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_8WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_9 |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_9ColdResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_9ForcedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_9ForcedFlippedBits |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_9ReadMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_9ResetMask |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_9ResetValue |
uint32_t |
VC TX Descriptor Table Address Register |
VCTXDADDR_9WriteMask |
uint32_t |
VC TX Descriptor Table Address Register |
config.irq |
uint8_t |
Interrupt number |
config.littleEndian |
uint8_t |
Endianess of memory interface. |
config.numDMAChannels |
uint8_t |
Number of DMA channels/engines available (1-8). |
config.numExternalFIFOs |
uint8_t |
Number of external FIFO interfaces available (0-32). |
config.numRXDescs |
uint32_t |
Number of RX descriptors held in VCRXDADDR tables (128, 256, 512 or 1024). |
config.numTXDescs |
uint32_t |
Number of TX descriptors held in VCTXDADDR tables (64, 128, 256 or 512). |
config.numVirtualChannels |
uint8_t |
Number of virtual channels available (1-32). |
externalFIFOs |
[temu_IfaceRef; 32]/ <unknown> |
External FIFO interfaces (e.g. for connections to the GRSPWROUTER) |
irqCtrl |
temu_IfaceRef/ <unknown> |
IRQ controller. |
packetQueues |
[temu_Vector; 33] |
Reception Packet queues |
pnp.bar |
uint32_t |
AMBA plug and play base address register |
pnp.config |
uint32_t |
AMBA plug and play config word |
Interfaces
| Name | Type | Description |
|---|---|---|
ApbIface |
ApbIface |
APB P&P interface. |
DeviceIface |
DeviceIface |
|
MemAccessIface |
MemAccessIface |
|
RegisterIface |
temu::RegisterIface |
Auto-generated Register Interface Impl. |
SpfiPortIface |
temu::SpfiPortIface |
SpaceFibre Port Interface of this device. |
Registers
| Register support is currently experimental! |
Register Bank Regs
Register GENCAP
- Description
-
Codec General Capabilities Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x1fffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
NEB |
|
|
Number of External Broadcast channels |
NEV |
|
|
Number of External Virtual channels |
WBWC |
|
|
Width of the bandwidth credit counter |
RFC |
|
|
Width of the remote FCT counter |
FCTM |
|
|
FCT multiplier |
NVC |
|
|
Number of Virtual Channels |
PI |
|
|
PRBS INIT1 |
BM |
|
|
16/20 bit mode selector |
IED |
|
|
Internal 8b10b encoder/decoder |
SCK |
|
|
Use separate clock for TX |
Register BUFCAP
- Description
-
Codec Buffers Capabilities Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VT |
|
|
Depth of the VC TX buffer |
VR |
|
|
Depth of the VC RX buffer |
RTB |
|
|
Depth of the Broadcast retry buffer |
RTF |
|
|
Depth of the FCT retry buffer |
RTD |
|
|
Depth of the Data retry buffer |
Register CCTRL
- Description
-
Codec Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00003fff
| Field | Mask | Reset | Description |
|---|---|---|---|
SCR |
|
|
Scramble enable |
LB |
|
|
Loop-back mode |
SBR |
|
|
Standby reason |
AS |
|
|
Auto-start |
LS |
|
|
Lane start |
LNR |
|
|
Lane reset |
LIR |
|
|
Link reset |
Register LLSTAT
- Description
-
Lane Layer Status Register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00fff58f
| Field | Mask | Reset | Description |
|---|---|---|---|
FEC |
|
|
Far end capabilities |
REC |
|
|
RX error words count |
REO |
|
|
RX error count overflow |
RXP |
|
|
RX polarity |
TO |
|
|
Timeout |
FELC |
|
|
Far-end loss of signal cause |
FEL |
|
|
Far-end loss of signal |
FES |
|
|
Far-end standby |
FER |
|
|
Far-end link reset |
LSTS |
|
|
Lane state |
Register RLSTAT
- Description
-
Retry Layer Status Register
- Reset value
-
0x00000400
- Warm reset mask
-
0x000004f0
| Field | Mask | Reset | Description |
|---|---|---|---|
RBE |
|
|
Retry buffer empty |
PE |
|
|
Protocol error |
TME |
|
|
Too many errors |
RTC |
|
|
Retry count |
SE |
|
|
Sequence error |
FE |
|
|
Frame error |
C8E |
|
|
CRC-8 error |
CE |
|
|
CRC-16 error |
Register DEFADDR
- Description
-
Default Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
DEFMSK |
|
|
Default mask |
DEFADDR |
|
|
Default address |
Register TS
- Description
-
Time-slot Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x3fffff3f
| Field | Mask | Reset | Description |
|---|---|---|---|
CNT |
|
|
Time-slot internal counter |
TS |
|
|
Time-slot |
Register TSCTRL
- Description
-
Time-slot Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00003ffd
| Field | Mask | Reset | Description |
|---|---|---|---|
ADJ |
|
|
Adjustment |
AS |
|
|
Adjustment sign |
AV |
|
|
Adjustment valid |
EG |
|
|
Enable internal generation of time-slots |
Register TSLEN
- Description
-
Time-slot Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x001fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
NOMLEN |
|
|
Time-slot nominal length |
Register BCCONF
- Description
-
Broadcast Channel Configuration Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffff01ff
| Field | Mask | Reset | Description |
|---|---|---|---|
BW |
|
|
Broadcast channel bandwidth |
BD |
|
|
Bypass DMA engine |
CHN |
|
|
Broadcast channel number |
Register DLCAP
- Description
-
DMA Layer Capabilities Register
- Reset value
-
0x80000000
- Warm reset mask
-
0x8000077f
| Field | Mask | Reset | Description |
|---|---|---|---|
SPFI |
|
|
SpaceFibre protocol implemented |
CC |
|
|
CCSDS CRC logic implemented |
RC |
|
|
RMAP CRC logic implemented |
RT |
|
|
RMAP target implemented |
NDMA |
|
|
Number of DMA channels |
NTXD |
|
|
Number of TX descriptors |
NRXD |
|
|
Number of RX descriptors |
Register DLCTRL
- Description
-
DMA Layer Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000007
| Field | Mask | Reset | Description |
|---|---|---|---|
BTE |
|
|
Broadcast TX interrupt enable |
BRE |
|
|
Broadcast RX interrupt enable |
LE |
|
|
Link interrupt enable |
Register DLSTAT
- Description
-
DMA Layer Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
DCI |
|
|
DMA channel interrupt |
TO |
|
|
AHB register timeout |
BT |
|
|
Broadcast transmission |
BR |
|
|
Broadcast reception |
LE |
|
|
Link event |
Register SPFIEN
- Description
-
SpaceFibre Enable Register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000001
| Field | Mask | Reset | Description |
|---|---|---|---|
EN |
|
|
SpaceFibre enable |
Register BCTXADDR
- Description
-
Broadcast Channel TX Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffc00
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
Broadcast channel TX buffer address |
Register BCTXSIZE
- Description
-
Broadcast Channel TX Size Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000ffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
SIZE |
|
|
Broadcast channel TX buffer size |
Register BCTXWPTR
- Description
-
Broadcast Channel TX Write Pointer Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000ffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
WRPTR |
|
|
Broadcast channel TX write pointer |
Register BCTXRPTR
- Description
-
Broadcast Channel TX Read Pointer Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000ffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
RDPTR |
|
|
Broadcast channel TX read pointer |
Register BCRXADDR
- Description
-
Broadcast Channel RX Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffc00
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
Broadcast channel RX buffer address |
Register BCRXSIZE
- Description
-
Broadcast Channel RX Size Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000ffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
SIZE |
|
|
Broadcast channel RX buffer size |
Register BCRXWPTR
- Description
-
Broadcast Channel RX Write Pointer Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000ffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
WRPTR |
|
|
Broadcast channel RX write pointer |
Register BCRXRPTR
- Description
-
Broadcast Channel RX Read Pointer Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000ffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
RDPTR |
|
|
Broadcast channel RX read pointer |
Register BCMAP
- Description
-
Broadcast Channel Mapping Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000001f
| Field | Mask | Reset | Description |
|---|---|---|---|
MAP |
|
|
Broadcast channel mapping |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register VCCTRL
- Description
-
Virtual Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffff1fb
| Field | Mask | Reset | Description |
|---|---|---|---|
VBW |
|
|
Virtual channel bandwidth |
PR |
|
|
Priority |
EFC |
|
|
External FIFO channel |
BD |
|
|
Bypass DMA engine |
RE |
|
|
RMAP enable |
AE |
|
|
Virtual channel address enable |
Register VCSTAT
- Description
-
Virtual Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
FCO |
|
|
FCT counter overflow |
IBO |
|
|
Input buffer overrun |
DHC |
|
|
Destination has credit |
BUU |
|
|
Bandwidth under-use |
BOU |
|
|
Bandwidth over-use |
Register VCMAXLEN
- Description
-
Virtual Channel RX Max Length Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MAXLGTH |
|
|
Virtual channel RX maximum length |
Register VCADDR
- Description
-
Virtual Channel Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMSK |
|
|
Virtual channel mask |
VCADDR |
|
|
Virtual channel address |
Register VCTS1
- Description
-
Virtual Channel Time-slot 1 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT1 |
|
|
Virtual channel time-slot 1 |
Register VCTS2
- Description
-
Virtual Channel Time-slot 2 Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSLOT2 |
|
|
Virtual channel time-slot 2 |
Register VCKEY
- Description
-
Virtual Channel Destination Key Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
KEY |
|
|
Virtual channel key |
Register VCTXDADDR
- Description
-
VC TX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff0
| Field | Mask | Reset | Description |
|---|---|---|---|
TXADDR |
|
|
TX descriptor table address and selector |
Register VCRXDADDR
- Description
-
VC RX Descriptor Table Address Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
RXADDR |
|
|
RX descriptor table address and selector |
Register VCDCTRL
- Description
-
Virtual Channel Descriptor Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xc0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TDA |
|
|
Transmit descriptor available |
RDA |
|
|
Receive descriptor available |
CTD |
|
|
Clear transmit descriptor table |
CRD |
|
|
Clear receive descriptor table |
NTD |
|
|
New transmit descriptor available |
NRD |
|
|
New receive descriptor available |
Register DCCTRL
- Description
-
DMA Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TS |
|
|
Transmitter stop |
RS |
|
|
Receiver stop |
TE |
|
|
Transmitter enable |
RE |
|
|
Receiver enable |
Register DCSTAT
- Description
-
DMA Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
RD |
|
|
RMAP done |
BMEVC |
|
|
Bus master error virtual channel |
BMEDSC |
|
|
Bus master error descriptor |
BMECD |
|
|
Bus master error code |
TX |
|
|
Packet transmitted |
RX |
|
|
Packet received |
TA |
|
|
Transmitter active |
RA |
|
|
Receiver active |
Register DCMAP
- Description
-
DMA Channel VC Mapping Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMAP |
|
|
DMA channel virtual channel mapping |
Register DCICTRL
- Description
-
DMA Channel IRQ Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
RMI |
|
|
RMAP interrupt enable |
BEI |
|
|
Bus master error interrupt enable |
TI |
|
|
Transmit interrupt enable |
RI |
|
|
Receive interrupt enable |
Register DCSTAT2
- Description
-
DMA Channel Extended Status Register
- Reset value
-
0x000001c1
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
RC |
|
|
RMAP counter |
TAF |
|
|
TX FIFO almost full |
TF |
|
|
TX FIFO full |
TS |
|
|
TX start |
TFS |
|
|
TX FSM state |
RAE |
|
|
RX FIFO almost empty |
RE |
|
|
RX FIFO empty |
RS |
|
|
RX start |
RFS |
|
|
RX FSM state |
Register DCCTRL
- Description
-
DMA Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TS |
|
|
Transmitter stop |
RS |
|
|
Receiver stop |
TE |
|
|
Transmitter enable |
RE |
|
|
Receiver enable |
Register DCSTAT
- Description
-
DMA Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
RD |
|
|
RMAP done |
BMEVC |
|
|
Bus master error virtual channel |
BMEDSC |
|
|
Bus master error descriptor |
BMECD |
|
|
Bus master error code |
TX |
|
|
Packet transmitted |
RX |
|
|
Packet received |
TA |
|
|
Transmitter active |
RA |
|
|
Receiver active |
Register DCMAP
- Description
-
DMA Channel VC Mapping Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMAP |
|
|
DMA channel virtual channel mapping |
Register DCICTRL
- Description
-
DMA Channel IRQ Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
RMI |
|
|
RMAP interrupt enable |
BEI |
|
|
Bus master error interrupt enable |
TI |
|
|
Transmit interrupt enable |
RI |
|
|
Receive interrupt enable |
Register DCSTAT2
- Description
-
DMA Channel Extended Status Register
- Reset value
-
0x000001c1
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
RC |
|
|
RMAP counter |
TAF |
|
|
TX FIFO almost full |
TF |
|
|
TX FIFO full |
TS |
|
|
TX start |
TFS |
|
|
TX FSM state |
RAE |
|
|
RX FIFO almost empty |
RE |
|
|
RX FIFO empty |
RS |
|
|
RX start |
RFS |
|
|
RX FSM state |
Register DCCTRL
- Description
-
DMA Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TS |
|
|
Transmitter stop |
RS |
|
|
Receiver stop |
TE |
|
|
Transmitter enable |
RE |
|
|
Receiver enable |
Register DCSTAT
- Description
-
DMA Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
RD |
|
|
RMAP done |
BMEVC |
|
|
Bus master error virtual channel |
BMEDSC |
|
|
Bus master error descriptor |
BMECD |
|
|
Bus master error code |
TX |
|
|
Packet transmitted |
RX |
|
|
Packet received |
TA |
|
|
Transmitter active |
RA |
|
|
Receiver active |
Register DCMAP
- Description
-
DMA Channel VC Mapping Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMAP |
|
|
DMA channel virtual channel mapping |
Register DCICTRL
- Description
-
DMA Channel IRQ Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
RMI |
|
|
RMAP interrupt enable |
BEI |
|
|
Bus master error interrupt enable |
TI |
|
|
Transmit interrupt enable |
RI |
|
|
Receive interrupt enable |
Register DCSTAT2
- Description
-
DMA Channel Extended Status Register
- Reset value
-
0x000001c1
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
RC |
|
|
RMAP counter |
TAF |
|
|
TX FIFO almost full |
TF |
|
|
TX FIFO full |
TS |
|
|
TX start |
TFS |
|
|
TX FSM state |
RAE |
|
|
RX FIFO almost empty |
RE |
|
|
RX FIFO empty |
RS |
|
|
RX start |
RFS |
|
|
RX FSM state |
Register DCCTRL
- Description
-
DMA Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TS |
|
|
Transmitter stop |
RS |
|
|
Receiver stop |
TE |
|
|
Transmitter enable |
RE |
|
|
Receiver enable |
Register DCSTAT
- Description
-
DMA Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
RD |
|
|
RMAP done |
BMEVC |
|
|
Bus master error virtual channel |
BMEDSC |
|
|
Bus master error descriptor |
BMECD |
|
|
Bus master error code |
TX |
|
|
Packet transmitted |
RX |
|
|
Packet received |
TA |
|
|
Transmitter active |
RA |
|
|
Receiver active |
Register DCMAP
- Description
-
DMA Channel VC Mapping Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMAP |
|
|
DMA channel virtual channel mapping |
Register DCICTRL
- Description
-
DMA Channel IRQ Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
RMI |
|
|
RMAP interrupt enable |
BEI |
|
|
Bus master error interrupt enable |
TI |
|
|
Transmit interrupt enable |
RI |
|
|
Receive interrupt enable |
Register DCSTAT2
- Description
-
DMA Channel Extended Status Register
- Reset value
-
0x000001c1
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
RC |
|
|
RMAP counter |
TAF |
|
|
TX FIFO almost full |
TF |
|
|
TX FIFO full |
TS |
|
|
TX start |
TFS |
|
|
TX FSM state |
RAE |
|
|
RX FIFO almost empty |
RE |
|
|
RX FIFO empty |
RS |
|
|
RX start |
RFS |
|
|
RX FSM state |
Register DCCTRL
- Description
-
DMA Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TS |
|
|
Transmitter stop |
RS |
|
|
Receiver stop |
TE |
|
|
Transmitter enable |
RE |
|
|
Receiver enable |
Register DCSTAT
- Description
-
DMA Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
RD |
|
|
RMAP done |
BMEVC |
|
|
Bus master error virtual channel |
BMEDSC |
|
|
Bus master error descriptor |
BMECD |
|
|
Bus master error code |
TX |
|
|
Packet transmitted |
RX |
|
|
Packet received |
TA |
|
|
Transmitter active |
RA |
|
|
Receiver active |
Register DCMAP
- Description
-
DMA Channel VC Mapping Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMAP |
|
|
DMA channel virtual channel mapping |
Register DCICTRL
- Description
-
DMA Channel IRQ Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
RMI |
|
|
RMAP interrupt enable |
BEI |
|
|
Bus master error interrupt enable |
TI |
|
|
Transmit interrupt enable |
RI |
|
|
Receive interrupt enable |
Register DCSTAT2
- Description
-
DMA Channel Extended Status Register
- Reset value
-
0x000001c1
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
RC |
|
|
RMAP counter |
TAF |
|
|
TX FIFO almost full |
TF |
|
|
TX FIFO full |
TS |
|
|
TX start |
TFS |
|
|
TX FSM state |
RAE |
|
|
RX FIFO almost empty |
RE |
|
|
RX FIFO empty |
RS |
|
|
RX start |
RFS |
|
|
RX FSM state |
Register DCCTRL
- Description
-
DMA Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TS |
|
|
Transmitter stop |
RS |
|
|
Receiver stop |
TE |
|
|
Transmitter enable |
RE |
|
|
Receiver enable |
Register DCSTAT
- Description
-
DMA Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
RD |
|
|
RMAP done |
BMEVC |
|
|
Bus master error virtual channel |
BMEDSC |
|
|
Bus master error descriptor |
BMECD |
|
|
Bus master error code |
TX |
|
|
Packet transmitted |
RX |
|
|
Packet received |
TA |
|
|
Transmitter active |
RA |
|
|
Receiver active |
Register DCMAP
- Description
-
DMA Channel VC Mapping Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMAP |
|
|
DMA channel virtual channel mapping |
Register DCICTRL
- Description
-
DMA Channel IRQ Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
RMI |
|
|
RMAP interrupt enable |
BEI |
|
|
Bus master error interrupt enable |
TI |
|
|
Transmit interrupt enable |
RI |
|
|
Receive interrupt enable |
Register DCSTAT2
- Description
-
DMA Channel Extended Status Register
- Reset value
-
0x000001c1
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
RC |
|
|
RMAP counter |
TAF |
|
|
TX FIFO almost full |
TF |
|
|
TX FIFO full |
TS |
|
|
TX start |
TFS |
|
|
TX FSM state |
RAE |
|
|
RX FIFO almost empty |
RE |
|
|
RX FIFO empty |
RS |
|
|
RX start |
RFS |
|
|
RX FSM state |
Register DCCTRL
- Description
-
DMA Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TS |
|
|
Transmitter stop |
RS |
|
|
Receiver stop |
TE |
|
|
Transmitter enable |
RE |
|
|
Receiver enable |
Register DCSTAT
- Description
-
DMA Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
RD |
|
|
RMAP done |
BMEVC |
|
|
Bus master error virtual channel |
BMEDSC |
|
|
Bus master error descriptor |
BMECD |
|
|
Bus master error code |
TX |
|
|
Packet transmitted |
RX |
|
|
Packet received |
TA |
|
|
Transmitter active |
RA |
|
|
Receiver active |
Register DCMAP
- Description
-
DMA Channel VC Mapping Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMAP |
|
|
DMA channel virtual channel mapping |
Register DCICTRL
- Description
-
DMA Channel IRQ Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
RMI |
|
|
RMAP interrupt enable |
BEI |
|
|
Bus master error interrupt enable |
TI |
|
|
Transmit interrupt enable |
RI |
|
|
Receive interrupt enable |
Register DCSTAT2
- Description
-
DMA Channel Extended Status Register
- Reset value
-
0x000001c1
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
RC |
|
|
RMAP counter |
TAF |
|
|
TX FIFO almost full |
TF |
|
|
TX FIFO full |
TS |
|
|
TX start |
TFS |
|
|
TX FSM state |
RAE |
|
|
RX FIFO almost empty |
RE |
|
|
RX FIFO empty |
RS |
|
|
RX start |
RFS |
|
|
RX FSM state |
Register DCCTRL
- Description
-
DMA Channel Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TS |
|
|
Transmitter stop |
RS |
|
|
Receiver stop |
TE |
|
|
Transmitter enable |
RE |
|
|
Receiver enable |
Register DCSTAT
- Description
-
DMA Channel Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
RD |
|
|
RMAP done |
BMEVC |
|
|
Bus master error virtual channel |
BMEDSC |
|
|
Bus master error descriptor |
BMECD |
|
|
Bus master error code |
TX |
|
|
Packet transmitted |
RX |
|
|
Packet received |
TA |
|
|
Transmitter active |
RA |
|
|
Receiver active |
Register DCMAP
- Description
-
DMA Channel VC Mapping Register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VCMAP |
|
|
DMA channel virtual channel mapping |
Register DCICTRL
- Description
-
DMA Channel IRQ Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
RMI |
|
|
RMAP interrupt enable |
BEI |
|
|
Bus master error interrupt enable |
TI |
|
|
Transmit interrupt enable |
RI |
|
|
Receive interrupt enable |
Register DCSTAT2
- Description
-
DMA Channel Extended Status Register
- Reset value
-
0x000001c1
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
RC |
|
|
RMAP counter |
TAF |
|
|
TX FIFO almost full |
TF |
|
|
TX FIFO full |
TS |
|
|
TX start |
TFS |
|
|
TX FSM state |
RAE |
|
|
RX FIFO almost empty |
RE |
|
|
RX FIFO empty |
RS |
|
|
RX start |
RFS |
|
|
RX FSM state |
Limitations
GRSPFI ignores any incoming flow control token (FTC) control words, and does not send out any FTCs either.
It has a virtually infinitely large receive buffer for every virtual channel, but will never send out any FTCs to the other end in order to communicate that.
When GRSPFI sends out packets, it will ignore any FTCs received for the channel it wants to send over. Even if the other side indicates that this channel has ran out of credits for a VC, GRSPFI will send packets.